DSP56366 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56366

Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Chip Errata

DSP56366 Digital Signal Processor

Mask:2J26D

Errata

Number

ES94

cont.

Errata Description

- option 3

Applies

to Mask

2J26D

bset #M_TE,x:M_TCSR0

movep #$848254,x:M_DCR3

transfer

bclr #M_TE,x:M_TCSR0

;; enable timer

;; enable DMA channel 3, block

;; mode, DE is disabled at the end of

;; the transfer, triggered by Timer0

;; (TCF0=1)

;; disable timer

Following are the differences between these three options:

option 1 : The DMA channel should be enabled only for the first block transfer. An

additional block transfers can be triggered by the following sequence:

bset

nop

nop

bclr

Note:

#M_TE,x:M_TCSR0

#M_TE,x:M_TCSR0

;; enable timer

;; disable timer

Execution of this sequence can be interrupted because the DMA channel is triggered

after the TE bit of the TCSR0 register is set. The TE bit must be cleared no later than

33554430 DSP clock cycles after it is set. Otherwise, an undesirable trigger for the

DMA channel is generated. The DMA channel must be disabled every time when

Timer 0 is used for another purpose.

option 2 : The whole sequence must be used every time when a block transfer is to

be triggered.

Note:

Execution of this sequence may be interrupted because the DMA channel is

triggered after the TE bit of the TCSR0 register is set. The TE bit must be cleared

no later than 33554430 DSP clock cycles after is is set. Otherwise, an undesirable

trigger for the DMA channel is generated.

option 3: The whole sequence must be used every time a block transfer is to be

triggered.

DSP56366 Errata

 1997 -2001, Motorola

For Mor3e66ICnfEo2rJm26aDt_io0n_0On This Product,

Go to: www.freescale.com

NG 11/12/01 pg. 8 of 25

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