DSP56371 View Datasheet(PDF) - Motorola => Freescale
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DSP56371 Datasheet PDF : 102 Pages
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Freescale Semiconductor, Inc.
Reset, Stop, Mode Select, and Interrupt Timing
Table 6 Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
Characteristics
Expression
Min Max Unit
20
• Delay from IRQA, IRQB, IRQC,
IRQD, NMI assertion to
general-purpose transfer output
valid caused by first interrupt
instruction execution
10 x TC + 3.0
59.0 ns
21 Interrupt Requests Rate
• ESAI, ESAI_1, SHI, DAX, Timer
12 x TC
—
—
ns
• DMA
8 x TC
—
—
ns
• IRQ, NMI (edge trigger)
8 x TC
—
—
ns
• IRQ (level trigger)
12 c TC
—
—
ns
22 DMA Requests Rate
• Data read from ESAI, ESAI_1,
SHI, DAX
6 x TC
—
—
ns
• Data write to ESAI, ESAI_1, SHI,
DAX
7 x TC
—
—
ns
• Timer
2 x TC
—
—
ns
• IRQ, NMI (edge trigger)
3 x TC
—
—
ns
Note:
1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings
19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the
deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are
recommended when using Level-sensitive mode.
2. For PLL disable, using external clock (PCTL Bit 13 = 0), no stabilization delay is required and recovery
time will be defined by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from
Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be
in the range of 0.5 ms.
3. Periodically sampled and not 100% tested
4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the
EXTAL input is active and valid. When the VDD is valid, but the other “required RESET duration”
conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized
state that can result in significant power consumption and heat-up. Designs should minimize this state
to the shortest possible duration.
8
DSP56371 Technical Data
MOTOROLA
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