DSP56374 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56374

24-Bit Audio Digital Signal Processor

Motorola => Freescale 

Features

5

15*

12

12*

3

SHI

Interface

GPIO

ESAI ESAI_1

Interface Interface

Triple

Timer

Watch

dog

Timer

Memory Expansion Area

Program

RAM

6k × 24

X Data

RAM

6k × 24

Y Data

RAM

6k × 24

Address

Generation

Unit

Six Channel

DMA Unit

Bootstrap

ROM

Peripheral

Expansion Area

ROM

20k × 24

ROM

4k × 24

YAB

XAB

PAB

DAB

24-Bit

DSP56300

Core

ROM

4k × 24

Internal

Data

Bus

Switch

DDB

YDB

XDB

PDB

GDB

Power

Clock

Gen.

PLL

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

Data ALU

24 × 24+56→56-bit MAC

Two 56-bit Accumulators

Mgmt.

JTAG

OnCE

4

56-bit Barrel Shifter

XTAL

EXTAL

RESET

PINIT/NMI

MODA/IRQA/GPIO

MODB/IRQB/GPIO

MODC/IRQC/GPIO

MODD/IRQD/GPIO

* ESAI_1 and dedicated GPIO pins are not available in the 52-pin package.

Figure 1. DSP56374 Block Diagram

1

Features

1.1

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DSP56300 Modular Chassis

150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V.

Object Code Compatible with the 56K core.

Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmatic support.

Program Control with position independent code support.

Six-channel DMA controller.

Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or

4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise

Internal address tracing support and OnCE for Hardware/Software debugging.

JTAG port, supporting boundary scan, compliant to IEEE 1149.1.

Very low-power CMOS design, fully static design with operating frequencies down to DC.

STOP and WAIT low-power standby modes.

2

PRELIMINARY

Freescale Semiconductor

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