DSP56374 View Datasheet(PDF) - Motorola => Freescale
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DSP56374 Datasheet PDF : 128 Pages
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Reset, Stop, Mode Select, and Interrupt Timing
Table 20. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
No.
Characteristics
Expression
Min Max Unit
19 Duration of level sensitive IRQA assertion to ensure
interrupt service (when exiting Stop)1, 2, 3
• PLL is active during Stop and Stop delay is
enabled
(OMR Bit 6 = 0)
9+(128× TC)
854 — µs
• PLL is active during Stop and Stop delay is not
enabled
(OMR Bit 6 = 1)
25× TC
165 — ns
• PLL is not active during Stop and Stop delay is
9+(128xTC) + TLOCK
5.7
ms
enabled (OMR Bit 6 = 0)
• PLL is not active during Stop and Stop delay is
(25 x TC) + TLOCK
5
ms
not enabled (OMR Bit 6 = 1)
20
• Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to general-purpose transfer output
valid caused by first interrupt instruction
execution1
21 Interrupt Requests Rate1
• ESAI, ESAI_1, SHI, Timer
10 x TC + 3.0
69.0 ns
12 x TC
— 80.0 ns
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
22 DMA Requests Rate
• Data read from ESAI, ESAI_1, SHI
8 x TC
8 x TC
12 x TC
6 x TC
— 53.0 ns
— 53.0 ns
— 80.0 ns
— 40.0 ns
• Data write to ESAI, ESAI_1, SHI
7 x TC
— 46.7 ns
• Timer
2 x TC
— 13.4 ns
• IRQ, NMI (edge trigger)
3 x TC
— 20.0 ns
Note:
1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when
using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be
defined by the OMR Bit 6 settings.
For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the
PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms.
3. Periodically sampled and not 100% tested.
4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active
and valid. When the VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been
yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up.
Designs should minimize this state to the shortest possible duration.
Freescale Semiconductor
PRELIMINARY
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