DSP56374 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56374

24-Bit Audio Digital Signal Processor

Motorola => Freescale 

Signal Groupings

3.1 Power

Table 4. Power Inputs

Power Name

Description

PLLA_VDD (1)

PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with

an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate

external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a

filter as shown in Figure 21 and Figure 22 below. See the DSP56374 technical data sheet for

additional details.

PLLP_VDD(1)

PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with

an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate

external decoupling capacitors between PLLP_VDD and PLLP_GND.

PLLD_VDD (1)

PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided

with an extremely low impedance path to the 1.25 VDD power rail. The user must provide

adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.

CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided

with an extremely low impedance path to the 1.25 VDD power rail. The user must provide

adequate external decoupling capacitors.

IO_VDD

(80-pin 4)

(52-pin 3)

SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,

and the input should be provided with an extremely low impedance path to the 3.3 VDD power

rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must

provide adequate external decoupling capacitors.

3.2 Ground

Table 5. Grounds

Ground Name

Description

PLLA_GND(1)

PLL Ground—The PLL ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.

PLLP_GND(1)

PLL Ground—The PLL ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.

PLLD_GND(1)

PLL Ground—The PLL ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.

CORE_GND(4) Core Ground—The Core ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors.

IO_GND(2)

SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,

ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground

connections. The user must provide adequate external decoupling capacitors.

Freescale Semiconductor

PRELIMINARY

5

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