DSP56374 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56374

24-Bit Audio Digital Signal Processor

Motorola => Freescale 

Signal Groupings

Signal Name

RESET

Table 8. Interrupt and Mode Control (Continued)

Type

Input

State

during

Reset

Signal Description

Input

Reset—RESET is an active-low, Schmitt-trigger input. When asserted,

the chip is placed in the Reset state and the internal phase generator is

reset. The Schmitt-trigger input allows a slowly rising input (such as a

capacitor charging) to reset the chip reliably. When the RESET signal is

de-asserted, the initial chip operating mode is latched from the MODA,

MODB, MODC, and MODD inputs. The RESET signal must be

asserted during power up. A stable EXTAL signal must be supplied

while RESET is being asserted.

This pin has an internal pull up resistor.

This input is 5 V tolerant.

3.6 Serial Host Interface

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.

Table 9. Serial Host Interface Signals

Signal

Name

SCK

SCL

Signal Type

State during

Reset

Signal Description

Input or output

Input or output

Tri-stated

SPI Serial Clock—The SCK signal is an output when the SPI is configured

as a master and a Schmitt-trigger input when the SPI is configured as a

slave. When the SPI is configured as a master, the SCK signal is derived

from the internal SHI clock generator. When the SPI is configured as a

slave, the SCK signal is an input, and the clock signal from the external

master synchronizes the data transfer. The SCK signal is ignored by the

SPI if it is defined as a slave and the slave select (SS) signal is not

asserted. In both the master and slave SPI devices, data is shifted on one

edge of the SCK signal and is sampled on the opposite edge where data is

stable. Edge polarity is determined by the SPI transfer protocol.

I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C

mode. SCL is a Schmitt-trigger input when configured as a slave and an

open-drain output when configured as a master. SCL should be connected

to VDD through an external pull-up resistor according to the I2C

specifications.

This signal is tri-stated during hardware, software, and individual reset.

This pin has an internal pull up resistor.

This input is 5 V tolerant.

8

PRELIMINARY

Freescale Semiconductor

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