DSP56100 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56100

16-bit General Purpose Digital Signal Processor

Motorola => Freescale 

HOST INTERFACE (15 PINS)

H0-H7 (Host Data Bus) — This bidirectional data bus is used

to transfer data between the host processor and the DSP.

This bus is an input unless enabled by a host processor

read. H0-H7 may be programmed as general purpose

parallel I/O pins called PB0-PB7 when the Host Interface

(HI) is not being used.

HA0-2 (Host Address 0-2) — These inputs provide the

address selection for each HI register and should be stable

when HEN is asserted. HA0-HA2 may be programmed as

general purpose parallel I/O pins called PB8-PB10 when

the HI is not being used.

HR/W (Host Read/Write) — This input selects the direction of

data transfer for each host processor access. If HR/W is

high and HEN is asserted, H0-H7 are outputs and DSP

data is transferred to the host processor. If HR/W is low and

HEN is asserted, H0-H7 are inputs and host data is

transferred to the DSP. HR/W should be stable when HEN

is asserted. HR/W may be programmed as a general

purpose I/O pin called PB11 when the HI is not being used.

HEN (Host Enable) — This input enables a data transfer on

the host data bus. When HEN is asserted and HR/W is

high, H0-H7 becomes an output and DSP data may be

latched by the host processor. When HEN is asserted and

HR/W is low, H0-H7 is an input and host data is latched

inside the DSP when HEN is deasserted. Normally a chip

select signal derived from host address decoding and an

enable clock is connected to the Host Enable. HEN may be

programmed as a general purpose I/O pin called PB12

when the HI is not being used.

HREQ (Host Request) — This open-drain output signal is

used by the HI to request service from the host processor.

HREQ may be connected to an interrupt request pin of a

host processor, a transfer request of a DMA controller, or a

control input of external circuitry. HREQ is asserted when

an enabled request occurs in the HI. HREQ is deasserted

when the enabled request is cleared or masked, DMA

HACK is asserted, or the DSP is reset. HREQ may be

programmed as a general purpose I/O pin (not open-drain)

called PB13 when the HI is not being used.

HACK (Host Acknowledge) — This input has two functions -

(1) to provide a Host Acknowledge signal for DMA transfers

or (2) to control handshaking and to provide a Host Interrupt

Acknowledge compatible with MC68000 family processors.

If programmed as a Host Acknowledge signal, HACK may

be used as a data strobe for HI DMA data transfers. If

programmed as an MC68000 Host Interrupt Acknowledge,

HACK is used to enable the HI Interrupt Vector Register

(IVR) onto the Host Data Bus H0-H7 if the Host Request

HREQ output is asserted. In this case, all other HI control

pins are ignored and the HI state is not affected. HACK may

be programmed as a general purpose I/O pin called PB14

when the HI is not being used.

16-BIT TIMER (2 PINS)

TIN

(Timer input) — This input receives external pulses to

be counted by the on-chip 16-bit timer when external

clocking is selected. The pulses are internally synchronized

to the DSP core internal clock. TIN may be programmed as

a general purpose I/O pin called PC10 when the external

event function is not being used.

TOUT (Timer output) — This output generates pulses or

toggles on a timer overflow event or a compare event.

TOUT may be programmed as a general purpose I/O pin

called PC11 when disabled by the timer out enable bits

(TO2-TO0).

SYNCHRONOUS SERIAL INTERFACES

(RSSI0 AND RSSI1) (8 PINS)

STD0/PC0 (RSSI0 Transmit Data) — This output pin

transmits serial data from the RSSI0 Transmit Shift

Register. STD0 may be programmed as a general purpose

I/O pin called PC0 when the RSSI0 STD0 function is not

being used.

SRD0/PC1 (RSSI0 Receive Data) — This input pin receives

serial data and transfers the data to the RSSI0 Receive

Shift Register. SRD0 may be programmed as a general

purpose I/O pin called PC1 when the RSSI0 SRD0 function

is not being used.

SCK0/PC2 (RSSI0 Serial Clock) — This bidirectional pin

provides the serial bit rate clock for the RSSI0 interface.

The clock signal can be continuous or gated and is used by

both the transmitter and receiver. SCK0 may be

programmed as a general purpose I/O pin called PC2 when

the RSSI0 interface is not being used.

SFS0/PC4 (Serial Frame Sync 0) — This bidirectional pin is

used by the RSSI0 serial interface as frame sync I/O or flag

I/O. The SFS0 is used by both the transmitter and receiver

to synchronize the data transfer of the data. It can be input

or output. SFS0 may be programmed as a general purpose

I/O pin called PC4 when the RSSI0 is not using this pin.

STD1/PC5 (RSSI1 Transmit Data) — This output pin

transmits serial data from the RSSI1 Transmit Shift

Register. STD1 may be programmed as a general purpose

I/O pin called PC5 when the RSSI1 STD1 function is not

being used.

SRD1/PC6 (RSSI1 Receive Data) — This input pin receives

serial data and transfers the data to the RSSI1 Receive

Shift Register. SRD1 may be programmed as a general

purpose I/O pin called PC6 when the RSSI1 SRD function

is not being used.

SCK1/PC7 (RSSI1 Serial Clock) — This bidirectional pin

provides the serial bit rate clock for the RSSI1 interface.

The clock signal can be continuous or gated and is used by

both the transmitter and receiver. SCK1 may be

programmed as a general purpose I/O pin called PC7 when

the RSSI1 interface is not being used.

SFS1/PC9 (Serial Frame Sync 1) — This bidirectional pin is

used by the RSSI1 serial interface as frame sync I/O or flag

I/O. The SFS1 is used by both the transmitter and receiver

to synchronize the data transfer of the data. It can be input

or output. SFS1 may be programmed as a general purpose

I/O pin called PC9 when the RSSI1 is not using this pin.

MOTOROLA

8

PRELIMINARY

DSP56166

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