DSP56156 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56156

16-bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

Electrical Characteristics and Timing

Analog I/O Characteristics

Analog I/O Characteristics

(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C)

The analog I/O characteristics of this device are listed in Table 7.

For additional information regarding the use of analog signals, see “Design Considerations”

at the end of this document.

Table 7 Analog I/O Characteristics

Characteristic

Min

Typ

Max

Unit

Input Impedance on MIC and AUX

(See Note 1)

Input Capacitance on MIC and AUX

Peak Input Voltage on the MIC/AUX Input for Full Scale

Linearity (0.14 dBm0):

6 dB - MGS1 - 0 = 00

(See Note 2)

0 dB - MGS1 - 0 = 01

6 dB - MGS1 - 0 = 10

17 dB - MGS1 - 0 = 11

Internal Input Gain Variation;

G = -6 dB, 0 dB, 6 dB or 17 dB

(±0.83 dB variation due to 10% variation on VCC):

VREF Output Voltage

VREF Output Current

DC Offset Between SPKP and SPKM

Allowable Differential Load Capacitance on

SPKP and SPKM (with 1 kΩ in series)

Allowable Single-ended Load Capacitance on

SPKP or SPKM (with 0.5 kΩ in series)

Maximum Single-ended Signal Output Level

Maximum Differential Signal Output Level

Single-ended Load Resistance

Differential Load Resistance

Resistance BIAS

Internal Output Volume Control Variation

VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB

(± 0.83 dB variation due to 10% variation on VCC)

46

—

—

—

—

—

G - 0.83

78

1400

—

10

—

1.414

—

0.707

—

354

—

100

G

G + 0.83

1.8

2

2.2

—

—

±1

—

—

100

0

—

0.05

0

(See Note 3)

—

—

500

1

—

VC - 0.83

—

100

0.1

—

1

—

2

—

—

—

—

10

—

(See

Note 4)

VC VC + 0.83

kΩ

pF

Vp

Vp

mVp

mVp

dB

V

mA

mV

µF

µF

Vp

Vp

Ω

kΩ

kΩ

dB

NOTES: 1. Minimum value reached for a Codec clock of 3 MHz, typical for 2 MHz and maximum for 100 kHz

2. 0 dBm0 corresponds to 3.14 dB below the input saturation level

3. AC coupling is necessary in single-ended mode when the load resistor is not tied to VREF

4. ± 10%

16

DSP56156 Data Sheet

MOTOROLA

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