Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 14 Wait and Stop Timings
Num
Characteristics
40 MHz
Min
Max
50 MHz
Min
Max
60 MHz
Unit
Min
Max
30 DR Asserted to CLK high (Setup
Time for Synchronous Recovery
10
cyc - 4
9
cyc - 3
8
cyc - 2 ns
from Wait State)
31 CLK high to DSO (ACK) Valid
(Enter Debug Mode) after Syn-
chronous Recovery from Wait
18 cyc
—
18 cyc
—
18 cyc
—
ns
State
32 DR to DSO (ACK) Valid
(Enter Debug Mode)
- After Asynchronous Recovery
from Stop State
29 cyc
—
29 cyc
—
29 cyc
—
ns
- After Asynchronous Recovery
from Wait State
18 cyc
—
18 cyc
—
18 cyc
—
ns
33 DR Assertion Width
- to Recover from Wait/Stop
without entering debug mode
12
10 cyc
11
10 cyc
10
10 cyc ns
- to Recover from Wait/Stop
short wake-up and enter
29 cyc
—
29 cyc
—
29 cyc
—
ns
debug mode
- to Recover from Stop
long wake-up and enter
debug mode
262157
—
262157
—
262157
—
ns
cyc
cyc
cyc
33
DR
(input)
32
DSO
(output)
Figure 15 Recovery from Wait State Using DR Pin — Synchronous Timing
MOTOROLA
DSP56156 Data Sheet
27
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