PRELIMINARY - 6/15/93
AC Electrical Characteristics — RSSI Timing (Continued)
Num
Characteristic
140 SCK Rising Edge to SFS Out (bl)
High
141 SCK Rising Edge to SFS Out
(wl) High
142 SCK Rising Edge to SFS Out
Low
143 SCK Rising Edge to Data Out
Enable from High Impedance
144 SCK Rising Edge to Data Out
Valid
145 SCK Rising Edge to Data Out
Invalid
146 SCK Rising Edge to Data Out
High Impedance
60MHz
Case Unit
Min Max
—
TBD i ck
ns
—
TBD i ck
ns
—
TBD i ck
ns
—
TBD i ck
ns
—
TBD i ck
ns
—
TBD i ck
ns
—
TBD i ck
ns
NOTES:
1. For internal clock, Serial Clock Cycle is defined by Icyc and RSSI control register.
41
DSP56166 Technical Data Sheet
MOTOROLA