DSP56166 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
DSP56166 Datasheet PDF : 63 Pages
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regains control of the external address bus, data bus, and
bus control pins until the BB pin is sampled high.
This pin becomes an input if the bus arbitration mode bit in
the OMR register is set (Master Mode). It is asserted by an
external processor when the DSP may become the bus
master. The DSP can start normal external memory access
after the BB pin has been deasserted by the previous bus
master. When BG is deasserted, the DSP will release the
bus as soon as the current transfer is completed. The state
of BG may be tested by testing the BS bit in the Bus Control
Register.
BG is ignored during hardware reset.
BB
(Bus Busy) — active low input when not bus master,
active low output when bus master. This pin is asserted by
the DSP when it becomes the bus master and it performs
an external access. It is deasserted when the DSP releases
bus mastership. BB becomes an input when the DSP is no
longer the bus master.
INTERRUPT AND MODE CONTROL (4 PINS)
MODA/IRQA (Mode Select A/External Interrupt Request A)
— This input has two functions - to select the initial chip
operating mode and, after synchronization, to allow an
external device to request a DSP interrupt. MODA is read
and internally latched in the DSP when the processor exits
the reset state. MODA and MODB select the initial chip
operating mode. Several clock cycles after leaving the reset
state, the MODA pin changes to the external interrupt
request IRQA. The chip operating mode can be changed by
software after reset. The IRQA input is a synchronized
external interrupt request which indicates that an external
device is requesting service. It may be programmed to be
level sensitive or negative edge triggered. If level sensitive
triggering is selected, an external pull up resistor is required
for wired-OR operation. If the processor is in the stop
standby state and IRQA is asserted, the processor will exit
the stop state.
MODB/IRQB (Mode Select B/External Interrupt Request B)
— This input has two functions - to select the initial chip
operating mode and, after internal synchronization, to allow
an external device to request a DSP interrupt. MODB is
read and internally latched in the DSP when the processor
exits the reset state. MODA and MODB select the initial
chip operating mode. Several clock cycles after leaving the
reset state, the MODB pin changes to the external interrupt
request IRQB. After reset, the chip operating mode can be
changed by software. The IRQB input is an external
interrupt request which indicates that an external device is
requesting service. It may be programmed to be level
sensitive or negative edge triggered. If level sensitive
triggering is selected, an external pull up resistor is required
for wired-OR operation.
MODC/IRQC (Mode Select C/External Interrupt Request C)
— This input has two functions - to select the initial bus
operating mode and after internal synchronization, to allow
an external device to request a DSP interrupt. MODC is
read and internally latched in the DSP when the processor
exits the RESET state.When tied high, the external bus is
programmed in the master mode (BR output and BG input)
and when tied low the bus is programmed in the slave mode
(BR input and BG output). After RESET, the bus operating
mode can be changed by software writing the MC bit of the
OMR register. Several clock cycles after leaving the
RESET state, the MODC pin changes to the external
interrupt request IRQC. The IRQC input is an external
interrupt request which indicates that an external device is
requesting service. It may be programmed to be level
sensitive or negative edge triggered. If level sensitive
triggering is selected, an external pull up resistor is required
for wired-OR operation.
RESET (Reset) — This input is a direct hardware reset of the
processor. When RESET is asserted, the DSP is initialized
and placed in the reset state. A Schmitt trigger input is used
for noise immunity. When the reset pin is deasserted, the
initial chip operating mode is latched from the MODA and
MODB pins. The internal reset signal is deasserted
synchronously with the internal clocks.
POWER, GROUND, AND CLOCK (28
PINS)
VDD (8) (Power) — power pins.
VSS (15) (Ground) — ground pins.
VDDS (Synthesizer Power) — This pin supplies a quiet
power source to the PLL to provide greater frequency
stability.
GNDS (Synthesizer Ground) — This pin supplies a quiet
ground source to the PLL to provide greater frequency
stability.
VDDA (Power Supply input) — This pin is the positive analog
supply input. It should be connected to VCC when the
codec is not used.
VSSA (Analog Ground) — This pin is the analog ground
return. It should be connected to VSS when the codec is not
used.
EXTAL (External Clock/Crystal Input) — This input should be
connected to an external clock or to an external oscillator.
A sine wave with a minimum swing of 1Vpp can be applied
to this pin. After being squared, the input frequency can be
used as the DSP core internal clock. In that case, it is
divided by two to produce a four phase instruction cycle
clock, the minimum instruction time being two input clock
periods.This input frequency is also used, after division, as
input clock for the on-chip codec and the on-chip phase
locked loop (PLL).
CLKO (Clock Output) — This pin outputs a buffered clock
signal. By programming two bits (CS1-CS0) inside the PLL
Control Register (PLCR), the user can select between
outputting a squared version of the signal applied to
EXTAL, a squared version of the signal applied to EXTAL
divided by 2, and a delayed version of the DSP core master
clock. The clock frequency on this pin can be disabled by
setting the Clockout Disable bit (CD; bit 7) of the Operating
Mode Register (OMR). In this case, the pin is driven low
and can be left floating.
SXFC (External Filter Capacitor) — This pin is used to add
an external capacitor to the PLL filter circuit. A low leakage
capacitor should be connected between SXFC and VDDS;
it should be located very close to those pins.
DSP56166
PRELIMINARY
MOTOROLA
7
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