DSP56303UM View Datasheet(PDF) - Freescale Semiconductor
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DSP56303UM Datasheet PDF : 108 Pages
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AC Electrical Characteristics
Table 2-12. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1,2
100 MHz
No.
Characteristics
Symbol
Expression3
Min Max
157 Random read or write cycle time
tRC
16 × TC
160.0
158 RAS assertion to data valid (read)
tRAC
8.25 × TC −5.7
—
159 CAS assertion to data valid (read)
tCAC
4.75 × TC −5.7
—
160 Column address valid to data valid (read)
tAA
5.5 × TC −5.7
—
161 CAS deassertion to data not valid (read hold time)
tOFF
0.0
0.0
162 RAS deassertion to RAS assertion
tRP
6.25 × TC −4.0
58.5
163 RAS assertion pulse width
tRAS
9.75 × TC −4.0
93.5
164 CAS assertion to RAS deassertion
tRSH
6.25 × TC −4.0
58.5
165 RAS assertion to CAS deassertion
tCSH
8.25 × TC −4.0
78.5
166 CAS assertion pulse width
tCAS
4.75 × TC −4.0
43.5
167 RAS assertion to CAS assertion
tRCD
3.5 × TC ± 2
33.0
168 RAS assertion to column address valid
tRAD
2.75 × TC ± 2
25.5
169 CAS deassertion to RAS assertion
tCRP
7.75 × TC −4.0
73.5
170 CAS deassertion pulse width
tCP
6.25 × TC – 6.0
56.5
171 Row address valid to RAS assertion
tASR
6.25 × TC −4.0
58.5
172 RAS assertion to row address not valid
tRAH
2.75 × TC −4.0
23.5
173 Column address valid to CAS assertion
tASC
0.75 × TC −4.0
3.5
174 CAS assertion to column address not valid
tCAH
6.25 × TC −4.0
58.5
175 RAS assertion to column address not valid
tAR
9.75 × TC −4.0
93.5
176 Column address valid to RAS deassertion
tRAL
7 × TC −4.0
66.0
177 WR deassertion to CAS assertion
178 CAS deassertion to WR4 assertion
179 RAS deassertion to WR4 assertion
tRCS
tRCH
tRRH
5 × TC −3.8
46.2
1.75 × TC – 3.7
13.8
0.25 × TC −2.0
0.5
180 CAS assertion to WR deassertion
tWCH
6 × TC −4.2
55.8
181 RAS assertion to WR deassertion
tWCR
9.5 × TC −4.2
90.8
182 WR assertion pulse width
tWP
15.5 × TC −4.5
150.5
183 WR assertion to RAS deassertion
tRWL
15.75 × TC −4.3
153.2
184 WR assertion to CAS deassertion
tCWL
14.25 × TC −4.3
138.2
185 Data valid to CAS assertion (write)
tDS
8.75 × TC −4.0
83.5
186 CAS assertion to data not valid (write)
tDH
6.25 × TC −4.0
58.5
187 RAS assertion to data not valid (write)
tDHR
9.75 × TC −4.0
93.5
188 WR assertion to CAS assertion
tWCS
9.5 × TC −4.3
90.7
189 CAS assertion to RAS assertion (refresh)
tCSR
1.5 × TC −4.0
11.0
190 RAS deassertion to CAS assertion (refresh)
tRPC
4.75 × TC −4.0
43.5
191 RD assertion to RAS deassertion
tROH
15.5 × TC −4.0
151.0
192 RD assertion to data valid
193 RD deassertion to data not valid5
tGA
14 × TC −5.7
—
tGZ
0.0
194 WR assertion to data active
0.75 × TC – 1.5
6.0
195 WR deassertion to data high impedance
0.25 × TC
—
Notes: 1. The number of wait states for an out-of-page access is specified in the DRAM Control Register.
2. The refresh period is specified in the DRAM Control Register.
3. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) .
4. Either tRCH or tRRH must be satisfied for read cycles.
5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
—
76.8
41.8
49.3
—
—
—
—
—
—
37.0
29.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
134.3
—
—
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
DSP56303 Technical Data, Rev. 11
2-21
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