DSP56303UM View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56303UM

24-Bit Digital Signal Processor

Freescale Semiconductor 

Signals/Connections

1.3 Clock

Signal Name

Type

EXTAL

Input

XTAL

Output

Table 1-4. Clock Signals

State During

Reset

Input

Chip-driven

Signal Description

External Clock/Crystal Input—Interfaces the internal crystal oscillator input

to an external crystal or an external clock.

Crystal Output—Connects the internal crystal oscillator output to an external

crystal. If an external clock is used, leave XTAL unconnected.

1.4 PLL

Signal Name

Type

CLKOUT

Output

PCAP

PINIT

NMI

Input

Input

Input

Table 1-5. Phase-Locked Loop Signals

State During

Reset

Chip-driven

Signal Description

Clock Output—Provides an output clock synchronized to the internal core

clock phase.

If the PLL is enabled and both the multiplication and division factors equal one,

then CLKOUT is also synchronized to EXTAL.

Input

Input

If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.

PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.

Connect one capacitor terminal to PCAP and the other terminal to VCCP.

If the PLL is not used, PCAP can be tied to VCC, GND, or left floating.

PLL Initial—During assertion of RESET, the value of PINIT is written into the

PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether

the PLL is enabled or disabled.

Nonmaskable Interrupt—After RESET deassertion and during normal

instruction processing, this Schmitt-trigger input is the negative-edge-triggered

NMI request internally synchronized to CLKOUT.

Note: PINIT/NMI can tolerate 5 V.

1.5 External Memory Expansion Port (Port A)

Note: When the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-

states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.

1.5.1 External Address Bus

Table 1-6. External Address Bus Signals

Signal Name

A[0–17]

Type

Output

State During

Reset, Stop, or

Wait

Signal Description

Tri-stated

Address Bus—When the DSP is the bus master, A[0–17] are active-high outputs that

specify the address for external program and data memory accesses. Otherwise, the

signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when

external memory spaces are not being accessed.

DSP56303 Technical Data, Rev. 11

1-4

Freescale Semiconductor

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