DSP56300 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56300

24-Bit Digital Signal Processor

Freescale Semiconductor 

1.5.2 External Data Bus

External Memory Expansion Port (Port A)

Signal

Name

Type

D[0–23] Input/ Output

Table 1-7. External Data Bus Signals

State

During

Reset

Ignored Input

State

During Stop

or Wait

Signal Description

Last state:

Input: Ignored

Output:

Tri-stated

Data Bus—When the DSP is the bus master, D[0–23] are active-high,

bidirectional input/outputs that provide the bidirectional data bus for external

program and data memory accesses. Otherwise, D[0–23] are tri-stated.

1.5.3 External Bus Control

Table 1-8. External Bus Control Signals

Signal

Name

AA[0–3]

Type

Output

State During Reset,

Stop, or Wait

Signal Description

Tri-stated

Address Attribute—When defined as AA, these signals can be used as chip selects or

additional address lines. The default use defines a priority scheme under which only

one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit

14) of the Operating Mode Register, the priority mechanism is disabled and the lines

can be used together as four external lines that can be decoded externally into 16 chip

select signals.

RAS[0–3] Output

RD

Output Tri-stated

WR

Output Tri-stated

TA

Input

Ignored Input

Row Address Strobe—When defined as RAS, these signals can be used as RAS for

DRAM interface. These signals are tri-statable outputs with programmable polarity.

Read Enable—When the DSP is the bus master, RD is an active-low output that is

asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is tri-

stated.

Write Enable—When the DSP is the bus master, WR is an active-low output that is

asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals

are tri-stated.

Transfer Acknowledge—If the DSP56309 is the bus master and there is no external

bus activity, or the DSP56309 is not the bus master, the TA input is ignored. The TA

input is a data transfer acknowledge (DTACK) function that can extend an external bus

cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the wait

states inserted by the bus control register (BCR) by keeping TA deasserted. In typical

operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion

of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle

completes one clock period after TA is asserted synchronous to CLKOUT. The number

of wait states is determined by the TA input or by the BCR, whichever is longer. The

BCR can be used to set the minimum number of wait states in external bus cycles.

To use the TA functionality, the BCR must be programmed to at least one wait state. A

zero wait state access cannot be extended by TA deassertion; otherwise, improper

operation may result. TA can operate synchronously or asynchronously depending on

the setting of the TAS bit in the Operating Mode Register. TA functionality cannot be

used during DRAM type accesses; otherwise improper operation may result.

BR

Output Reset: Output

Bus Request—Asserted when the DSP requests bus mastership. BR is deasserted

(deasserted)

when the DSP no longer needs the bus. BR may be asserted or deasserted

independently of whether the DSP56309 is a bus master or a bus slave. Bus “parking”

State during Stop/Wait allows BR to be deasserted even though the DSP56309 is the bus master. (See the

depends on BRH bit

description of bus “parking” in the BB signal description.) The bus request hold (BRH)

setting:

bit in the BCR allows BR to be asserted under software control even though the DSP

• BRH = 0: Output,

does not need the bus. BR is typically sent to an external bus arbitrator that controls the

deasserted

priority, parking, and tenure of each master on the same external bus. BR is affected

• BRH = 1: Maintains last only by DSP requests for the external bus, never for the internal bus. During hardware

state (that is, if asserted, reset, BR is deasserted and the arbitration is reset to the bus slave state.

remains asserted)

DSP56309 Technical Data, Rev. 7

Freescale Semiconductor

1-5

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