DSP56311 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56311 Datasheet PDF : 96 Pages
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Features
Table 1 lists the features of the DSP56311 device.
Table 1. DSP56311 Features
Feature
Description
High-Performance
DSP56300 Core
• Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering
applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
Enhanced Filter
Coprocessor (EFCOP)
• Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 150 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
• Real finite impulse response (FIR) with real taps
• Complex FIR with complex taps
• Complex FIR generating pure real or pure imaginary outputs alternately
• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
• Direct form 2 (DFII) IIR filter
• Four scaling factors (1, 4, 8, 16) for IIR output
• Adaptive FIR filter with true least mean square (LMS) coefficient updates
• Adaptive FIR filter with delayed LMS coefficient updates
Internal Peripherals
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
• 192 × 24-bit bootstrap ROM
• 128 K × 24-bit RAM total
:• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
Program Instruction X Data RAM Y Data RAM Instruction Switch
RAM Size Cache Size
Size*
Size*
Cache
Mode
MSW1 MSW0
32 K × 24-bit
0
48 K × 24-bit 48 K × 24-bit disabled disabled 0/1 0/1
31 K × 24-bit 1024 × 24-bit 48 K × 24-bit 48 K × 24-bit enabled disabled 0/1 0/1
96 K × 24-bit
0
16 K × 24-bit 16 K × 24-bit disabled enabled 0
0
Internal Memories
95 K × 24-bit 1024 × 24-bit 16 K × 24-bit 16 K × 24-bit enabled enabled 0
0
80 K × 24-bit
0
24 K × 24-bit 24 K × 24-bit disabled enabled 0
1
79 K × 24-bit 1024 × 24-bit 24 K × 24-bit 24 K × 24-bit enabled enabled 0
1
64 K × 24-bit
0
32 K × 24-bit 32 K × 24-bit disabled enabled 1
0
63 K × 24-bit 1024 × 24-bit 32 K × 24-bit 32 K × 24-bit enabled enabled 1
0
48 K × 24-bit
0
40 K × 24-bit 40 K × 24-bit disabled enabled 1
1
47 K × 24-bit 1024 × 24-bit 40 K × 24-bit 40 K × 24-bit enabled enabled 1
1
*Includes 10 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
iii
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