DSP56311 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56311

24-Bit Digital Signal Processor

Freescale Semiconductor 

Signals/Connections

1

The DSP56311 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1

diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in

each functional group.

Table 1-1. DSP56311 Functional Signal Groupings

Functional Group

Number of

Signals

Power (VCC)

20

Ground (GND)

66

Clock

2

PLL

3

Address bus

Data bus

18

Port A1

24

Bus control

13

Interrupt and mode control

Host interface (HI08)

Enhanced synchronous serial interface (ESSI)

Serial communication interface (SCI)

5

Port B2

16

Ports C and D3

12

Port E4

3

Timer

3

OnCE/JTAG Port

6

Notes: 1. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.

2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.

3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

5. There are 5 signal connections that are not used. These are designated as no connect (NC) in the package description (see

Chapter 3).

Note:

The Clock Output (CLKOUT), BCLK, BCLK, CAS, and RAS[0–3] signals used by other DSP56300 family members

are supported by the DSP56311 at operating frequencies up to 100 MHz. Therefore, above 100 MHz, you must

enable bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit (ABE) in the operating mode register.

When set, the ABE bit eliminates the required set-up and hold times for BB and BG with respect to CLKOUT. In

addition, DRAM access is not supported above 100 MHz.

DSP56311 Technical Data, Rev. 8

Freescale Semiconductor

1-1

Share Link: