DSP56311 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56311

24-Bit Digital Signal Processor

Freescale Semiconductor 

Power Consumption Benchmark

M_DRS EQU $F800

M_DCON EQU 16

M_DPR EQU $60000

M_DPR0 EQU 17

M_DPR1 EQU 18

M_DTM EQU $380000

M_DTM0 EQU 19

M_DTM1 EQU 20

M_DTM2 EQU 21

M_DIE EQU 22

M_DE EQU 23

; DMA Request Source Mask (DRS0-DRS4)

; DMA Continuous Mode

; DMA Channel Priority

; DMA Channel Priority Level (low)

; DMA Channel Priority Level (high)

; DMA Transfer Mode Mask (DTM2-DTM0)

; DMA Transfer Mode 0

; DMA Transfer Mode 1

; DMA Transfer Mode 2

; DMA Interrupt Enable bit

; DMA Channel Enable bit

;

DMA Status Register

M_DTD EQU $3F

M_DTD0 EQU 0

M_DTD1 EQU 1

M_DTD2 EQU 2

M_DTD3 EQU 3

M_DTD4 EQU 4

M_DTD5 EQU 5

M_DACT EQU 8

M_DCH EQU $E00

M_DCH0 EQU 9

M_DCH1 EQU 10

M_DCH2 EQU 11

; Channel Transfer Done Status MASK (DTD0-DTD5)

; DMA Channel Transfer Done Status 0

; DMA Channel Transfer Done Status 1

; DMA Channel Transfer Done Status 2

; DMA Channel Transfer Done Status 3

; DMA Channel Transfer Done Status 4

; DMA Channel Transfer Done Status 5

; DMA Active State

; DMA Active Channel Mask (DCH0-DCH2)

; DMA Active Channel 0

; DMA Active Channel 1

; DMA Active Channel 2

;------------------------------------------------------------------------

;

;

EQUATES for Enhanced Filter Co-Processor (EFCOP)

;

;------------------------------------------------------------------------

M_FDIR EQU

M_FDOR EQU

M_FKIR EQU

M_FCNT EQU

M_FCSR EQU

M_FACR EQU

M_FDBA EQU

M_FCBA EQU

M_FDCH EQU

$FFFFB0

$FFFFB1

$FFFFB2

$FFFFB3

$FFFFB4

$FFFFB5

$FFFFB6

$FFFFB7

$FFFFB8

; EFCOP Data Input Register

; EFCOP Data Output Register

; EFCOP K-Constant Register

; EFCOP Filter Counter

; EFCOP Control Status Register

; EFCOP ALU Control Register

; EFCOP Data Base Address

; EFCOP Coefficient Base Address

; EFCOP Decimation/Channel Register

;------------------------------------------------------------------------

;

;

EQUATES for Phase Locked Loop (PLL)

;

;------------------------------------------------------------------------

;

Register Addresses Of PLL

M_PCTL EQU $FFFFFD

; PLL Control Register

;

PLL Control Register

M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11)

M_DF EQU $7000

; Division Factor Bits Mask (DF0-DF2)

M_XTLR EQU 15

; XTAL Range select bit

M_XTLD EQU 16

; XTAL Disable Bit

M_PSTP EQU 17

; STOP Processing State Bit

M_PEN EQU 18

; PLL Enable Bit

A-12

DSP56311 Technical Data, Rev. 8

Freescale Semiconductor

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