DSP56321VL275 View Datasheet(PDF) - Freescale Semiconductor
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Description
Manufacturer
DSP56321VL275 Datasheet PDF : 84 Pages
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Specifications
Table 2-6. CLKGEN and DPLL Characteristics (Continued)
Characteristics
200 MHz
Symbol
Min Max
220 MHz
Min Max
240 MHz
Min Max
275 MHz
Min Max
Notes: 1. Refer to the DSP56321 User’s Manual for a detailed description of register reset values.
2. The total multiplication factor (MF) includes both integer and fractional parts (that is, MF = MFI + MFN/MFD).
3. The numerator (MFN) should be less than the denominator (MFD).
4. DPLL lock procedure duration is specified for the case when an external clock source is supplied to the EXTAL pin.
5. Frequency-only Lock Mode or non-integer MF, after partial reset.
6. Frequency and Phase Lock Mode, integer MF, after full reset.
Unit
2.4.4 Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing5
No.
Characteristics
8 Delay from RESET assertion to all
pins at reset value3
9 Required RESET duration4
• Power on, external clock
generator, DPLL disabled
• Power on, external clock
generator, DPLL enabled
• Power on, internal oscillator
• During STOP, XTAL disabled
• During STOP, XTAL enabled
• During normal operation
10 Delay from asynchronous RESET
deassertion to first external address
output (internal reset deassertion)
• Minimum
• Maximum
13 Mode select setup time
14 Mode select hold time
15 Minimum edge-triggered interrupt
request assertion width
16 Minimum edge-triggered interrupt
request deassertion width
17 Delay from IRQA, IRQB, IRQC, IRQD,
NMI assertion to external memory
access address out valid
• Caused by first interrupt instruction
fetch
• Caused by first interrupt instruction
execution
18 Delay from IRQA, IRQB, IRQC, IRQD,
NMI assertion to general-purpose
transfer output valid caused by first
interrupt instruction execution
19 Delay from address output valid
caused by first interrupt instruction
execute to interrupt request
deassertion for level sensitive fast
interrupts1, 6, 7
Expression
—
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
2.5 × TC
3.25 × TC + 2.0
4.25 × TC + 2.0
7.25 × TC + 2.0
8.9 × TC
(WS + 3.75) × TC –
10.94
200 MHz
Min Max
220 MHz
Min Max
240 MHz
Min Max
275 MHz
Unit
Min Max
—
26
—
26
—
26
—
26 ns
250.0 — 227.5 — 208.5 — 182.0 — ns
5.0 — 4.55 — 4.17 — 3.64 — µs
0.375 — 0.341 — 0.313 — 0.273 — ms
0.375 — 0.341 — 0.313 — 0.273 — ms
12.5 — 11.38 — 10.43 — 9.1 — ns
17
—
16
—
15
—
9.1
— ns
18.25 — 16.77 — 15.55 — 13.82 — ns
— 180 — 163 — 150 — 140 ns
30.0 — 30.0 — 30.0 — 30.0 — ns
0.0 — 0.0 — 0.0 — 0.0 — ns
4.0 — 4.0 — 4.0 — 4.0 — ns
4.0 — 4.0 — 4.0 — 4.0 — ns
23.25 — 21.24 — 19.72 — 17.45 — ns
38.25 — 34.99 — 32.23 — 28.36 — ns
44.5 — 40.45 — 37.0 — 32.37 — ns
— Note 7 — Note 7 — Note 7 — Note 7 ns
DSP56321 Technical Data, Rev. 11
2-6
Freescale Semiconductor
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