DSP56321 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56321

24-Bit Digital Signal Processor

Freescale Semiconductor 

M_PCOD EQU

0

M_PSTP EQU

1

M_XTLD EQU

2

M_PEN EQU

3

; PLL Clock Output Disable Bit

; STOP Processing State Bit

; XTAL Disable Bit

; PLL Enable Bit

;------------------------------------------------------------------------

;

;

EQUATES for BIU

;

;------------------------------------------------------------------------

;

Register Addresses Of BIU

M_BCR EQU $FFFFFB

M_DCR EQU $FFFFFA

M_AAR0 EQU $FFFFF9

M_AAR1 EQU $FFFFF8

M_AAR2 EQU $FFFFF7

M_AAR3 EQU $FFFFF6

M_IDR EQU $FFFFF5

; Bus Control Register

; DRAM Control Register

; Address Attribute Register 0

; Address Attribute Register 1

; Address Attribute Register 2

; Address Attribute Register 3

; ID Register

;

Bus Control Register

M_BA0W EQU $1F

M_BA1W EQU $3E0

M_BA2W EQU $1C00

M_BA3W EQU $E000

M_BDFW EQU $1F0000

M_BBS EQU 21

M_BLH EQU 22

M_BRH EQU 23

; Area 0 Wait Control Mask (BA0W0-BA0W4)

; Area 1 Wait Control Mask (BA1W0-BA14)

; Area 2 Wait Control Mask (BA2W0-BA2W2)

; Area 3 Wait Control Mask (BA3W0-BA3W3)

; Default Area Wait Control Mask (BDFW0-BDFW4)

; Bus State

; Bus Lock Hold

; Bus Request Hold

;

DRAM Control Register

M_BCW EQU $3

M_BRW EQU $C

M_BPS EQU $300

M_BPLE EQU 11

M_BME EQU 12

M_BRE EQU 13

M_BSTR EQU 14

M_BRF EQU $7F8000

M_BRP EQU 23

; In Page Wait States Bits Mask (BCW0-BCW1)

; Out Of Page Wait States Bits Mask (BRW0-BRW1)

; DRAM Page Size Bits Mask (BPS0-BPS1)

; Page Logic Enable

; Mastership Enable

; Refresh Enable

; Software Triggered Refresh

; Refresh Rate Bits Mask (BRF0-BRF7)

; Refresh prescaler

;

Address Attribute Registers

M_BAT EQU $3

M_BAAP EQU 2

M_BPEN EQU 3

M_BXEN EQU 4

M_BYEN EQU 5

M_BAM EQU 6

M_BPAC EQU 7

M_BNC EQU $F00

M_BAC EQU $FFF000

; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)

; Address Attribute Pin Polarity

; Program Space Enable

; X Data Space Enable

; Y Data Space Enable

; Address Muxing

; Packing Enable

; Number of Address Bits to Compare Mask (BNC0-BNC3)

; Address to Compare Bits Mask (BAC0-BAC11)

;

control and status bits in SR

M_CP EQU $c00000

M_CA EQU 0

M_V EQU 1

; mask for CORE-DMA priority bits in SR

; Carry

; Overflow

Freescale Semiconductor

DSP56321 Technical Data, Rev. 11

A-13

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