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DSP56362 View Datasheet(PDF) - Freescale Semiconductor

Part Name
Description
Manufacturer
DSP56362
Freescale
Freescale Semiconductor Freescale
DSP56362 Datasheet PDF : 152 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Overview
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active
when low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Examples:
Signal/Symbol
Logic State
Signal State
Voltage*
PIN
True
Asserted
PIN
False
Deasserted
PIN
True
Asserted
PIN
False
Deasserted
Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
VIL / VOL
VIH / VOH
VIH / VOH
VIL / VOL
2
16
12
5
Triple
Timer
DAX
Host
(SPDIF) Interface
ESAI
Program RAM/
Instruction
X Data
Y Data
SHI
Cache
RAM
RAM
3072 × 24 5632 × 24
Program ROM ROM
30K × 24 6144 ×
5632 ×
24
Memory
Expansion
Bootstrap ROM
192 × 24
24
ROM
6144 × 24
Area
Address
Generation
Unit
Six Channel
DMA Unit
Internal
Data
Bus
Switch
Peripheral
Expansion Area
YAB
XAB
PAB
DAB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
External
18
Address
Bus
Switch
Address
DRAM/SRAM
Bus
11
Interface
&
I - Cache Control
Control
External
Data Bus
Switch
24
Data
EXTAL
CLKOUT
Clock
Generator
PLL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Power
Mngmnt.
Program
Address
Generator
Data ALU
24 ¥ 24 + 56 Æ 56-bit MAC JTAG
Two 56-bit Accumulators
56-bit Barrel Shifter OnCE™
6
AA0456G
Figure 1-1 DSP56362 Block Diagram
DSP56362 Technical Data, Rev. 4
1-2
Freescale Semiconductor

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