DSP56366 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56366

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

5.5 Host Port Considerations

Careful synchronization is required when reading multi-bit registers that are written by another

asynchronous system. This synchronization is a common problem when two asynchronous systems are

connected, as they are in the host interface. The following paragraphs present considerations for proper

operation.

5.5.1 Host Programming Considerations

• Unsynchronized Reading of Receive Byte Registers—When reading the receive byte registers,

receive register high (RXH), receive register middle (RXM), or receive register low (RXL), the

host interface programmer should use interrupts or poll the receive register data full (RXDF) flag

that indicates whether data is available. This ensures that the data in the receive byte registers will

be valid.

• Overwriting Transmit Byte Registers—The host interface programmer should not write to the

transmit byte registers, transmit register high (TXH), transmit register middle (TXM), or transmit

register low (TXL), unless the transmit register data empty (TXDE) bit is set, indicating that the

transmit byte registers are empty. This ensures that the transmit byte registers will transfer valid

data to the host receive (HRX) register.

• Synchronization of Status Bits from DSP to Host—HC, HOREQ, DMA, HF3, HF2, TRDY,

TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor

(refer to the user’s manual for descriptions of these status bits). The host can read these status bits

very quickly without regard to the clock rate used by the DSP, but the state of the bit could be

changing during the read operation. This is not generally a system problem, because the bit will be read

correctly in the next pass of any host polling routine.

However, if the host asserts HEN for more than timing number 31, with

a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be

stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP

changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits

during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has

significance, the host could read the wrong combination. Therefore, read the bits twice and

check for consensus.

• Overwriting the Host Vector—The host interface programmer should change the host vector

(HV) register only when the host command (HC) bit is clear. This ensures that the DSP interrupt

control logic will receive a stable vector.

• Cancelling a Pending Host Command Exception—The host processor may elect to clear the HC

bit to cancel the host command exception request at any time before it is recognized by the DSP.

Because the host does not know exactly when the exception will be recognized (due to exception

processing synchronization and pipeline delays), the DSP may execute the host command

exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the

same time that the HC bit is cleared.

• Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL

lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make

DSP56366 Technical Data, Rev. 3.1

Freescale Semiconductor

5-5

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