DSP56366 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56366

24-Bit Audio Digital Signal Processor

Freescale Semiconductor 

2.6 Interrupt and Mode Control

The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.

After RESET is deasserted, these inputs are hardware interrupt request lines.

Table 2-8 Interrupt and Mode Control

Signal Name Type

State

during

Reset

Signal Description

MODA/IRQA Input

MODB/IRQB Input

MODC/IRQC Input

MODD/IRQD Input

Input

Input

Input

Input

Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into the OMR when the RESET signal is deasserted. If the processor is

in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will

exit the stop state.

This input is 5 V tolerant.

Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is deasserted.

This input is 5 V tolerant.

Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is deasserted.

This input is 5 V tolerant.

Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the

initial chip operating mode during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request input during normal instruction

processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating

modes, latched into OMR when the RESET signal is deasserted.

This input is 5 V tolerant.

RESET

Input

Input

Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed

in the Reset state and the internal phase generator is reset. The Schmitt-trigger input

allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When

the RESET signal is deasserted, the initial chip operating mode is latched from the

MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during

power up. A stable EXTAL signal must be supplied while RESET is being asserted.

This input is 5 V tolerant.

DSP56366 Technical Data, Rev. 3.1

2-8

Freescale Semiconductor

Share Link: