Reset, Stop, Mode Select, and Interrupt Timing
3.9 Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1
No.
Characteristics
8 Delay from RESET assertion to all pins at reset value2
9 Required RESET duration3
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Power on, Internal oscillator
• During STOP, XTAL disabled
• During STOP, XTAL enabled
• During normal operation
10 Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)4
• Minimum
• Maximum
Expression
—
50 × ETC
1000 × ETC
75000 × ETC
75000 × ETC
2.5 × TC
2.5 × TC
3.25 × TC + 2.0
20.25 × TC + 10
Min Max Unit
— 26.0 ns
333.4 —
ns
6.7
—
µs
500
—
µs
500
—
µs
16.7 —
ns
16.7 —
ns
ns
23.7 —
— 145.0
11 Syn reset setup time from RESET
• Maximum
12 Syn reset deassert delay time
• Minimum
• Maximum
13 Mode select setup time
TC
3.25 × TC + 1.0
20.25 × TC + 5.0
ns
—
6.7
ns
22.7 —
— 140.0
30.0 —
ns
14 Mode select hold time
0.0
—
ns
15 Minimum edge-triggered interrupt request assertion width
4.4
—
ns
16 Minimum edge-triggered interrupt request deassertion width
4.4
—
ns
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory access address out valid
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution
4.25 × TC + 2.0
7.25 × TC + 2.0
10 × TC + 5.0
ns
30.3 —
50.3 —
71.7 —
ns
19 Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for level
sensitive fast interrupts5, 6, 7
(WS + 3.75) × TC – 10.94
— Note 8 ns
20 Delay from RD assertion to interrupt request deassertion for (WS + 3.25) × TC – 10.94
level sensitive fast interrupts5, 6, 7
— Note 8 ns
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-7