DSP56374PB/D View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56374PB/D Datasheet PDF : 64 Pages
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Signal Groupings
Table 5. Grounds (continued)
Ground Name
Description
PLLP_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLLD_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
CORE_GND(4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND(2)
SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,
ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
4.3 SCAN
Signal
Name
SCAN
Type
Input
Table 6. SCAN Signals
State
During
Reset
Signal Description
Input SCAN—Manufacturing test pin. This pin must be connected to ground.
4.4 Clock and PLL
Table 7. Clock and PLL Signals
Signal
Name
EXTAL
XTAL
PINIT/NMI
Type
State
during
Reset
Signal Description
Input
Input
External Clock / Crystal Input—An external clock source must be connected
to EXTAL in order to supply the clock to the internal clock generator and PLL.
Output Chip Driven Crystal Output—Connects the internal Crystal Oscillator output to an external
crystal. If an external clock is used, leave XTAL unconnected.
Input
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET
de-assertion and during normal instruction processing, the PINIT/NMI
Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt
(NMI) request internally synchronized to the internal system clock.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
7
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