DSP56374UM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56374UM Datasheet PDF : 64 Pages
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Signal Groupings
Table 8. Interrupt and Mode Control (continued)
Signal Name
Type
State
during
Reset
Signal Description
PH2
MODD/IRQD
Input, output,
or
disconnected
Input
Port H2—When the MODC/IRQC is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
MODD
Input
Mode Select D/External Interrupt Request D—MODD/IRQD is an
active-low Schmitt-trigger input, internally synchronized to the DSP
clock. MODD/IRQD selects the initial chip operating mode during
hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input during
normal instruction processing. This pin can also be programmed as
GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip
operating modes, latched into OMR when the RESET signal is
de-asserted.
PH3
RESET
Input, output,
or
disconnected
Input
Input
This pin has an internal pull up resistor.
This input is 5 V tolerant.
Port H3—When the MODD/IRQD is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
Reset—RESET is an active-low, Schmitt-trigger input. When asserted,
the chip is placed in the Reset state and the internal phase generator is
reset. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET signal is
de-asserted, the initial chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET signal must be asserted
during power up. A stable EXTAL signal must be supplied while RESET
is being asserted.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
4.6 Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
9
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