E910.01 View Datasheet(PDF) - ELMOS Semiconductor AG

Part Name

Description

Manufacturer

E910.01

LOW SIDE DRIVER (8 CHANNEL, SERIAL INTERFACE)

ELMOS Semiconductor AG 

Low side driver (8 channel, serial interface)

PRODUCTION DATA - MaY 3, 2011

E910.01

4.2 Detailed Functional Description

This IC was specially developed for Automobile applications. Application areas include driving relays, Lamps, bus

systems etc. with medium power consumption. The E910.01 comprises a serial data bus and 8 identical power driv-

ers. All outputs are short circuit protected, and a thermal cut-off protects the devices from thermal overstress.

By means of the RESET signal (RESET=Low) the IC can be switched into a low current consumption mode (Sleep

Mode). In this mode all current consumption is disabled.

There are two possible data transfer protocols:

a) Parallel data input (see Figure 5 and Figure 9)

SI and SO are tied together and the device is activated by means of the chip enable (CE) line. On the falling edge

of the CE signal the data is loaded into the shift register and SO goes to the low impedance state. With each rising

edge of SCLK the data beginning with Bit 7 (D7) is clocked out at SO and with each falling edge new data is clocked

from SI. On the rising edge of CE the data from the shift register is clocked through to the outputs. SO goes to the

high impedance state (Tri-State as long as CE remains inactive HIGH). A LOW level on the input produces a LOW

level on the open drain driver which switches to the low impedance state.

RESET

CE1

CE2

CE3

SCLK

SI

SO

OUT(7:0)

E910.01

Reset CE SCLK SI SO

Figure 5: Parallel data input

OUT(7:0)

E910.01

Reset CE SCLK SI SO

OUT(7:0)

E910.01

Reset CE SCLK SI SO

b) Serial data input (see Figure 6 and Figure 7/8)

The complete Daisy Chain of drivers are enabled in parallel by CE and clocked out by SCLK. On the falling edge of

CE the status of each output is clocked into the shift register. On each rising edge of SCLK data is clocked out of SO,

and with each falling edge of SCLK new data is clocked into SI. After 8 x n clock cycles new data has been read in

and existing data clocked out. On the rising edge of CE new data is clocked through to the outputs. SO goes to the

high impedance state (Tri-state as long as CE remains inactive HIGH). A LOW level on the input produces a LOW

level on the open drain driver which switches to the low impedance state.

ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

ELMOS Semiconductor AG

Data Sheet

QM-No.: 25DS0038E.00

8/17

Share Link: