EBE21AE8ACWA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
EBE21AE8ACWA Datasheet PDF : 27 Pages
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EBE21AE8ACWA
Block Diagram
/RCS1
/RCS0
RS
/DQS0
RS
DQS0
RS
/DQS9
RS
DM0/DQS9
8 RS
DQ0 to DQ7
NU/ /CS DQS /DQS
/RDQS
DM/
RDQS D0
DQ0
to DQ7
NU/ /CS DQS /DQS
/RDQS
DM/
RDQS D9
DQ0
to DQ7
RS
/DQS1
RS
DQS1
RS
/DQS10
RS
DM1/DQS10
8 RS
DQ8 to DQ15
NU/
/RDQS
/CS DQS
/DQS
DM/
RDQS D1
DQ0
to DQ7
NU/
/RDQS
/CS DQS
/DQS
DM/
RDQS D10
DQ0
to DQ7
RS
/DQS2
RS
DQS2
RS
/DQS11
RS
DM2/DQS11
8 RS1
DQ16 to DQ23
NU/ /CS DQS /DQS
/RDQS
DM/
RDQS D2
DQ0
to DQ7
NU/ /CS DQS /DQS
/RDQS
DM/
RDQS D11
DQ0
to DQ7
RS
/DQS3
RS
DQS3
RS
/DQS12
RS
DM3/DQS12
8 RS
DQ24 to DQ31
RS
/DQS8
RS
DQS8
RS
/DQS17
RS
DM8/DQS17
CB0 to CB7
8 RS
NU/
/RDQS
/CS DQS
/DQS
DM/
RDQS D3
DQ0
to DQ7
NU/
/RDQS
/CS DQS
/DQS
DM/
RDQS D12
DQ0
to DQ7
NU/ /CS DQS /DQS
/RDQS
DM/
/RDQS D8
DQ0
to DQ7
NU/ /CS DQS /DQS
/RDQS
DM/
/RDQS D17
DQ0
to DQ7
RS
/DQS4
RS
DQS4
RS
/DQS13
RS
DM4/DQS13
8 RS
DQ32 to DQ39
RS
/DQS5
RS
DQS5
RS
/DQS14
RS
DM5/DQS14
8 RS
DQ40 to DQ47
RS
/DQS6
RS
DQS6
RS
/DQS15
RS
DM6/DQS15
8 RS
DQ48 to DQ55
RS
/DQS7
RS
DQS7
RS
/DQS16
RS
DM7/DQS16
8 RS
DQ56 to DQ63
NU/ /CS DQS /DQS
/RDQS
DM,
RDQS D4
DQ0
to DQ7
NU/ /CS DQS /DQS
/RDQS
DM,
RDQS D13
DQ0
to DQ7
NU/
/RDQS
/CS DQS
/DQS
DM/
/RDQS D5
DQ0
to DQ7
NU/
/RDQS
/CS DQS
/DQS
DM/
/RDQS D14
DQ0
to DQ7
NU/ /CS DQS /DQS
/RDQS
DM/
/RDQS D6
DQ0
to DQ7
NU/ /CS DQS /DQS
/RDQS
DM/
/RDQS D15
DQ0
to DQ7
NU/
/RDQS
/CSDQS /DQS
DM/
/RDQS D7
DQ0
to DQ7
NU/
/RDQS
/CSDQS /DQS
DM/
/RDQS D16
DQ0
to DQ7
/CS0*2 RS
/CS1*2 RS
BA0 to BA2 RS
A0 to A13 RS
/RAS RS
/CAS RS
CKE0 RS
RS
CKE1
RS
/WE
/ODT0 RS
/ODT1 RS
/RESET*3
PCK7*3
R
E
G
I
S
T
E
R
/RST
/RCS0 -> /CS: SDRAMs D0 to D8
/RCS1 -> /CS: SDRAMs D9 to D17
SCL
RBA0 to RBA2 -> BA0 to BA2: SDRAMs D0 to D17
RA0 to RA13 -> A0 to A13: SDRAMs D0 to D17
/RRAS -> /RAS: SDRAMs D0 to D17
/RCAS -> /CAS: SDRAMs D0 to D17
RCKE0 -> CKE: SDRAMs D0 to D8
VDDSPD
RCKE1 -> CKE: SDRAMs D9 to D17
VDD
/RWE -> /WE: SDRAMs D0 to D17
RODT0 -> ODT: SDRAMs D0 to D8
VREF
VSS
RODT1 -> ODT: SDRAMs D9 to D17
/PCK7*3
Notes:
1. DQ wiring may be changed within a byte.
2. /CS0 connects to /DCS on register1 and /CSR on register2.
/CS1 connects to /CSR on register1 and /DCS on register2.
3. /RESET, PCK7 and /PCK7 connect to all registers.
Other signals connect to one of two registers.
VSS
VDD
Par_In
100kΩ
Serial PD
SCL
SDA
U0
WP A0 A1 A2
SA0 SA1 SA2
SDA
D0 to D17: 1G bits DDR2 SDRAM
U0: 2k bits EEPROM
RS: 22Ω
PLL: CUA877
Register: SSTUB32866
Serial PD
CK0
P
/CK0
L
D0 to D17
L
D0 to D17 /RESET OE
D0 to D17
PCK0 to PCK6,PCK8,PCK9 -> CK: SDRAMs D0 to D17
/PCK0 to /PCK6,/PCK8,/PCK9 -> /CK: SDRAMs D0 to D17
PCK7 -> CK: register
/PCK7 -> /CK: register
Signals for Address and Command Parity Function
C0 Register A
C1
PAR_IN PPO
/QERR
VDD
VDD
C0 Register B
C1
PAR_IN
PPO
/QERR
/Err_Out
Data Sheet E1396E10 (Ver. 1.0)
8
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