EBE10EE8ACFA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
EBE10EE8ACFA Datasheet PDF : 30 Pages
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EBE10EE8ACFA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
(DDR2 SDRAM Component Specification)
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8E
-8G
-6E
Speed bin
DDR2-800 (5-5-5) DDR2-800 (6-6-6) DDR2-667 (5-5-5)
Parameter
Active to read or write command
delay
Precharge command period
Active to active/auto-refresh
command time
DQ output access time from CK,
/CK
DQS output access time from CK,
/CK
Symbol
tRCD
tRP
tRC
tAC
tDQSCK
min.
12.5
12.5
57.5
−400
−350
CK high-level width
tCH (avg) 0.48
max.
+400
+350
0.52
CK low-level width
CK half period
Clock cycle time
(CL = 6)
tCL(avg) 0.48
0.52
Min.
tHP
(tCL(abs),
tCH(abs))
tCK (avg) 2500
8000
min.
max.
15
15
60
−400
+400
−350
+350
0.48
0.52
0.48
0.52
Min.
(tCL(abs),
tCH(abs))
2500
8000
min.
max.
15
15
60
−450
+450
−400
+400
0.48
0.52
0.48
0.52
Min.
(tCL(abs),
tCH(abs))
3000
8000
Unit Notes
ns
ns
ns
ps 10
ps 10
tCK
(avg)
13
tCK
(avg)
13
ps 6, 13
ps 13
(CL = 5)
tCK (avg) 2500
8000
3000
8000
3000
8000
ps 13
(CL = 4)
tCK (avg) 3750
8000
3750
8000
3750
8000
ps 13
(CL = 3)
tCK (avg) 5000
8000
5000
8000
5000
8000
ps 13
DQ and DM input hold time
tDH
(base)
125
125
175
ps 5
DQ and DM input setup time
tDS
(base)
50
50
100
ps 4
Control and Address input pulse
width for each input
tIPW
0.6
0.6
0.6
tCK
(avg)
DQ and DM input pulse width for
each input
tDIPW
Data-out high-impedance
CK,/CK
time
from
tHZ
DQS, /DQS low-impedance time tLZ
from CK,/CK
(DQS)
0.35
0.35
0.35
tCK
(avg)
tAC max.
tAC max.
tAC max. ps 10
tAC min. tAC max. tAC min. tAC max. tAC min. tAC max. ps 10
DQ low-impedance time from
CK,/CK
DQS-DQ skew for DQS and
associated DQ signals
tLZ (DQ)
2
×
tAC
min.
tAC
max.
2
× tAC min
tAC max.
2
× tAC min
tAC max.
ps
10
tDQSQ
200
200
240
ps
DQ hold skew factor
tQHS
300
300
340
ps 7
DQ/DQS output hold time from
DQS
tQH
tHP –
tQHS
tHP –
tQHS
tHP –
tQHS
ps 8
DQS latching rising transitions to
associated clock edges
tDQSS
−0.25
+0.25
−0.25
+0.25
−0.25
+0.25
tCK
(avg)
DQS input high pulse width
tDQSH 0.35
DQS input low pulse width
tDQSL 0.35
DQS falling edge to CK setup time tDSS 0.2
0.35
0.35
0.2
0.35
0.35
0.2
tCK
(avg)
tCK
(avg)
tCK
(avg)
Data Sheet E1059E20 (Ver. 2.0)
18
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