EDS5104ABTA View Datasheet(PDF) - Elpida Memory, Inc
Part Name
Description
Manufacturer
EDS5104ABTA Datasheet PDF : 52 Pages
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EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
Current state
/CS /RAS /CAS /WE Address
Command
Operation
Mode register set
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10 READ/READA
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRITA
ILLEGAL*4
L
L
H
H
BA, RA
ACT
Bank and row active*9
L
L
H
L
BA, A10
L
L
L
H
×
L
L
L
L
MODE
PRE, PALL
REF, SELF
MRS
NOP
Refresh*9
Mode register set*8
Remark: H: VIH. L: VIL. ×: VIH or VIL
Notes: 1.An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if lMRD is not satisfied.
Preliminary Data Sheet E0250E10 (Ver. 1.0)
20
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