EL4584 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
EL4584 Datasheet PDF : 12 Pages
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Data Sheet
July 25, 2005
EL4584
FN7174.2
Horizontal Genlock, 4FSC
The EL4584 is a PLL (Phase Lock Loop) sub system,
designed for video applications but also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS compatible Pixel Clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 Sync Separator. An
input signal to “coast” is provided for applications were
periodic disturbances are present in the reference video
timing such as VTR head switching. The Lock detector
output indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards, by external
selection of three control pins. These four ratios have been
selected for common video applications including 4FSC,
3FSC, 13.5MHz (CCIR 601 format) and square picture
elements used in some workstation graphics. To generate
8FSC, 6FSC, 27MHz (CCIR 601 format) etc. use the
EL4585, which includes an additional divide-by-two stage.
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
FREQUENCIES AND DIVISORS
FUNCTION
3FSC CCIR 601 SQUARE
(NOTE 1) (NOTE 2) (NOTE 3)
Divisor
851
864
944
PAL FOSC (MHz) 13.301
13.5
Divisor
682
858
14.75
780
4FSC
1135
17.734
910
NTSC FOSC MHz) 10.738
13.5
12.273 14.318
NOTES:
1. 3FSC numbers do not yield integer divisors.
2. CCIR 601 Divisors yield 720 pixels in the portion of each line for
NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL in the active portion.
Features
• 36MHz, general purpose PLL
• 4FSC based timing (use the EL4585 for 8FSC)
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation
• Pb-Free plus anneal available (RoHS compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing
Ordering Information
PART NUMBER PACKAGE
TAPE & PKG. DWG.
REEL
#
EL4584CN
16-Pin PDIP
-
MDP0031
EL4584CS
16-Pin SO (0.150”)
-
MDP0027
EL4584CS-T7 16-Pin SO (0.150”)
7”
MDP0027
EL4584CS-T13 16-Pin SO (0.150”)
13”
MDP0027
EL4584CSZ
16-Pin SO (0.150”)
-
(See Note)
(Pb-free)
MDP0027
EL4584CSZ-T7 16-Pin SO (0.150”)
7”
(See Note)
(Pb-free)
MDP0027
EL4584CSZ-T13 16-Pin SO (0.150”)
13”
(See Note)
(Pb-free)
MDP0027
*For 6FSC and 8FSC clock frequencies, see EL4585 datasheet.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Demo Board
A demo PCB is available for this product.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc.2003-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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