EL4584 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
EL4584 Datasheet PDF : 12 Pages
| |||
EL4584
of a long pendulum. Due to parasitic effects of PCB traces
and component variables, it will take some trial and error
experimentation to determine the best values to use for any
given situation. Use the component tables as a starting
point, but be aware that deviation from these values is not
out of the ordinary.
External Divide
DIV SEL (pin 8) controls the use of the internal divider. When
high, the internal divider is enabled and EXT DIV (pin 13)
outputs the CLK out divided by N. This is the signal to which
the horizontal sync input will lock. When divide select is low,
the internal divider output is disabled, and external divide
becomes an input from an external divider, so that a divisor
other than one of the 8 pre-programmed internal divisors can
be used.
Normal Mode
Normal mode is enabled by pulling COAST (pin 9) low
(below 1/3*VCC). If HSYNC and CLK ÷ N have any phase or
frequency difference, an error signal is generated and sent
to the charge pump. The charge pump will either force
current into or out of the filter capacitor in an attempt to
modulate the VCO frequency. Modulation will continue until
the phase and frequency of CLK ÷ N exactly match the
HSYNC input. When the phase and frequency match (with
some offset in phase that is a function of the VCO
characteristics), the error signal goes to zero, lock detect no
longer pulses high, and the charge pump enters a high
impedance state. The clock is now locked to the HSYNC
input. As long as phase and frequency differences remain
small, the PLL can adjust the VCO to remain locked and lock
detect remains low.
Fast Lock Mode
Fast Lock mode is enabled by either allowing coast to float,
or pulling it to mid supply (between 1/3 and 2/3*VCC). In this
mode, lock is achieved much faster than in normal mode, but
the clock divisor is modified on the fly to achieve this. If the
phase detector detects an error of enough magnitude, the
clock is either inhibited or reset to attempt a “fast” lock of the
signals.
Forcing the clock to be synchronized to the HSYNC input this
way allows a lock in approximately 2 H-cycles, but the clock
spacing will not be regular during this time. Once the near
lock condition is attained, charge pump output should be
very close to its lock-on value and placing the device into
normal mode should result in a normal lock very quickly.
Fast Lock mode is intended to be used where HSYNC
becomes irregular, until a stable signal is again obtained.
Coast Mode
Coast mode is enabled by pulling COAST (pin 9) high
(above 2/3*VCC). In coast mode the internal phase detector
is disabled and filter out remains in high impedance mode to
keep filter out voltage and VCO frequency as constant a
possible. VCO frequency will drift as charge leaks from the
filter capacitor, and the voltage changes the VCO operating
point. Coast mode is intended to be used when noise or
signal degradation result in loss of horizontal sync for many
cycles. The phase detector will not attempt to adjust to the
resultant loss of signal so that when horizontal sync returns,
sync lock can be re-established quickly. However, if much
VCO drift has occurred, it may take as long to re-lock as
when restarting.
Lock Detect
Lock detect (pin 12) will go low when lock is established. Any
DC current path from charge pump out will skew EXT DIV
relative to HSYNC in, tending to offset or add to the 110ns
internal delay, depending on which way the extra current is
flowing. This offset is called static phase error, and is always
present in any PLL system. If, when the part stabilizes in a
locked mode, lock detect is not low, adding or subtracting
from the loop filter series resistor R2 will change this static
phase error to allow LDET to go low while in lock. The goal is
to put the rising edge of EXT DIV in sync with the falling
edge of HSYNC + 110ns. (See timing diagrams.) Increasing
R2 decreases phase error, while decreasing R2 increases
phase error. (Phase error is positive when EXT DIV lags
HSYNC.) The resistance needed will depend on VCO design
or VCXO module selection.
Applications Information
Choosing External Components
1. To choose LC VCO components, first pick the desired
operating frequency. For our example we will use
14.31818MHz, with an HSYNC frequency of 15.734kHz.
2. Choose a reasonable inductor value (10–20µH works
well). We choose 15µH.
3. Calculate CT needed to produce FOSC.
FOSC
=
-----------1-----------
2π LCT
CT
=
---------1-----------
4π2F2L
=
----------------------------------1-----------------------------------
4π2(14.318e6)2(15e – 6)
=
8.2 p F
4. From the varactor data sheet find CV @ 2.5V, the desired
lock voltage. CV = 23pF for our SMV1204-12, for
example.
5. C2 should be about 10CV, so we choose C2 = 220pF for
our example.
6. Calculate C1. Since:
CT = -(--C----1----C----2----)---+-----C(---C-1---1-C---C-2---V-C---)-V--+-----(---C----2----C----V----)---′
then:
C1 = -(--C-----2---C----V----)---–---(-C--C--2--2-C--C---T--T--C--)--V-–-----(--C-----T---C-----V----)--′
8
FN7174.2
July 25, 2005
Share Link: 