EL4585 View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

EL4585

Horizontal Genlock, 8FSC

Intersil 

Timing Diagrams

EL4585

H-SYNC

(INPUT)

~200ns ± 50ns

EXT. DIV.

(INPUT OR

OUTPUT)

PLL LOCKED CONDITION (PHASE ERROR = 0)

HSYNC

EXT. DIV

-

+

CHARGE

PUMP -OFF

~200ns

tH

t0

+

θE = tθtH × 360°

tH = HSYNC PERIOD

tθ = PHASE ERROR PERIOD

OFF

OUT OF LOCK CONDITION

Test Circuit

+

3

VOUT

-

0.1µF

VIN

5

10mVRMS

TEST CIRCUIT 1

5

FN7175.4

September 3, 2009

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