E-ETC5054D-X/HTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
E-ETC5054D-X/HTR Datasheet PDF : 18 Pages
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ETC5054 - ETC5057
TIMING SPECIFICATIONS
Symbol
1/tPM
tWMH
tWML
tRM
tFM
tPB
tWBH
tWBL
tRB
tFB
tSBFM
tHBF
tSFB
tHBFI
tDZF
tDBD
tDZC
tSDB
tHBD
tHOLD
tSF
tHF
tXDP
tWFL
Parameter
Frequency of master clocks
Depends on the device used and the BCLKR/CLKSEL Pin
MCLKX and MCLKR
Width of Master Clock High
MCLKX and MCLKR
Width of Master Clock Low
Rise Time of Master Clock
MCLKX and MCLKR
MCLKX and MCLKR
Fall Time of Master Clock
MCLKX and MCLKR
Period of Bit Clock
Width of Bit Clock High (VIH = 2.2V)
Width of Bit Clock Low (VIL = 0.6V)
Rise Time of Bit Clock (tPB = 488ns)
Fall Time of Bit Clock (tPB = 488ns)
Set-up time from BCLKX high to MCLKX falling edge.
(first bit clock after the leading edge of FSX)
Holding Time from Bit Clock Low to the Frame Sync
(long frame only)
Set-up Time from Frame Sync to Bit Clock (long frame only)
Hold Time from 3rd Period of Bit Clock
Low to Frame Sync (long frame only)
FSX or FSR
Delay time to valid data from FSX or BCLKX, whichever comes later
and delay time from FSX to data output disabled.
(CL = 0pF to 150pF)
Delay time from BCLKX high to data valid.
(load = 150pF plus 2 LSTTL loads)
Delay time from BCLKX low to data output disabled.
Set-up time from DR valid to BCLKR/X low.
Hold time from BCLKR/X low to DR invalid.
Holding Time from Bit Clock High to Frame Sync
(short frame only)
Set-up Time from FSX/R to BCLKX/R Low
(short frame sync pulse) - Note 1
Hold Time from BCLKX/R Low to FSX/R Low
(short frame sync pulse) - Note 1
Delay Time to TSXlow (load = 150pF plus 2 LSTTL loads)
Minimum Width of the Frame Sync Pulse (low level)
64kbit/s operating mode)
Min.
160
160
485
160
160
100
0
80
100
20
0
50
50
50
0
80
100
160
Typ.
1.536
1.544
2.048
Max.
50
50
488 15.725
50
50
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
165
ns
180
ns
165
ns
ns
ns
ns
ns
ns
140
ns
ns
Note 1: For short frame sync timing FSX and FSR must go high while their respective bit clocks are high.
Figure 1: 64kbits/s TIMING DIAGRAM (see next page for complete timing).
FSx
FSR
7/18
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