M27V402 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M27V402 Datasheet PDF : 15 Pages
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M27V402
Figure 6. Programming and Verify Modes AC Waveforms
A0-A17
Q0-Q15
tAVEL
DATA IN
VALID
DATA OUT
tQVEL
tEHQX
VPP
VCC
tVPHEL
tVCHEL
tGLQV
tGHQZ
tGHAX
E
tELEH
) G
tQXGL
uct(s PROGRAM
VERIFY
AI00730
te Prod Figure 7. Programming Flowchart
bsole VCC = 6.25V, VPP = 12.75V
) - O n = 0
duct(s NO
ro ++n
P = 25
te YES
ObsoleFAIL
E = 100µs Pulse
NO
VERIFY
YES
++ Addr
Last NO
Addr
YES
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at VCC much
higher than 3.6V provides necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27V402s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27V402 may be common. A TTL low level pulse
applied to a M27V402's E input, with VPP at
12.75V, will program that M27V402. A high level E
input inhibits the other M27V402s from being pro-
CHECK ALL WORDS
1st: VCC = 6V
2nd: VCC = 4.2V
grammed.
Program Verify
A verify (read) should be performed on the pro-
AI00726C
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
8/15
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