MT4C1004J883C View Datasheet(PDF) - Austin Semiconductor
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Description
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MT4C1004J883C Datasheet PDF : 14 Pages
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AUSTIN SEMICONDUCTOR, INC.
MMTT45CC1100045J 883C
4 M25E6GK xx 14 DSRAM
NOTES
1. All voltages referenced to VSS.
2. This parameter is sampled, not 100% tested.
Capacitance is measured with Vcc = 5V, f = 1 MHz at
less than 50mVrms, TA = 25°C ±3°C, Vbias = 2.4V
applied to each input and output individually with
remaining inputs and outputs open.
3. ICC is dependent on cycle rates.
4. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (-55°C ≤ TA ≤ 125°C) is assured.
7. An initial pause of 100µs is required after power-up
followed by eight /R?A/S refresh cycles (/R/A/S-ONLY or
CBR with ?/W/E HIGH) before proper device operation
is assured. The eight /R/A/S cycle wake-up should be
repeated any time the 16ms refresh requirement is
exceeded.
8. AC characteristics assume tT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If /C/A/S = VIH, data output is High-Z.
12. If /C/A/S = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to 2 TTL gates and
100pF.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that tRCD ≥ tRCD (MAX).
16. If /C/A/S is LOW at the falling edge of /R/A/S, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, /C/A/S must be
pulsed HIGH for tCPN.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by tCAC.
18. Operation within the tRAD (MAX) limit ensures that
tRCD (MAX) can be met. tRAD (MAX) is specified as
a reference point only; if tRAD is greater than the
specified tRAD (MAX) limit, then access time is
controlled exclusively by tAA.
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. tWCS, tRWD, tAWD and tCWD are restrictive
operating parameters in LATE WRITE, READ-WRITE
and READ-MODIFY-WRITE cycles only. If tWCS ≥
tWCS (MIN), the cycle is an EARLY-WRITE cycle and
the data output will remain an open circuit through-
out the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥
tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a
READ-WRITE and the data output will contain data
read from the selected cell. If neither of the above
conditions are met, the cycle is a LATE-WRITE and
the state of Q is indeterminate (at access time and
until /C/A/S goes back to VIH).
22. These parameters are referenced to /C/A/S leading edge
in EARLY-WRITE cycles and ?W/E leading edge in
LATE-WRITE or READ-WRITE cycles.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case ?W/E = LOW.
24. tWTS and tWTH are set up and hold specifications for
the ?W/E pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of tWRP and tWRH in the
CBR REFRESH cycle.
25. JEDEC test mode only.
MT4C1004J 883C
REV. 11/97
DS000021
2-29
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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