FIN1049(2013) View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

FIN1049
(Rev.:2013)

LVDS Dual-Line Driver with Dual-Line Receiver

Fairchild Semiconductor 

Required Specifications and Test Diagrams

Notes:

7. Electrostatic Discharge Capability: Human Body Model and Machine Model ESD should be measured using MIL-

STD-883C method 3015.7 standard.

8. Latch-up immunity should be tested to the EIA/JEDEC Standard Number 78 (EIA/JESD78).

Figure 3. Differential Receiver Voltage Definitions Test Circuit

Note:

9. CL=15 pF, includes all probe and jig capacitances.

Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages

Applied Voltages (V)

VIA

1.25

1.15

VCC

VCC - 0.1

0.1

0.0

1.75

0.65

VCC

VCC - 1.1

1.1

0.0

VIB

1.15

1.25

VCC - 0.1

VCC

0.0

0.1

0.65

1.75

VCC - 1.1

VCC

0.0

1.1

Resulting Differential

Input Voltage (mV)

VID

100

-100

100

-100

100

-100

1100

-1100

1100

-1100

1100

-1100

Resulting Common

Mode Input Voltage (V)

VIC

1.2

1.2

VCC - 0.05

VCC - 0.05

0.05

0.05

1.2

1.2

VCC - 0.55

VCC - 0.55

0.55

0.55

Note:

10. RL=100 

Figure 4. LVDS Output Circuit for DC Test

© 2003 Fairchild Semiconductor Corporation

FIN1049 • Rev. 1.0.3

6

www.fairchildsemi.com

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