TC7135CBU View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

TC7135CBU

4-1/2 digit A/D converter

Microchip Technology 

3.2.1 SYSTEM ZERO

During this phase, errors due to buffer, integrator and

comparator offset voltages are compensated for by

charging CAZ (auto-zero capacitor) with a compensat-

ing error voltage. With a zero input voltage, the

integrator output will remain at zero.

The external input signal is disconnected from the

internal circuitry by opening the two SWI switches. The

internal input points connect to the ANALOG

COMMON pin. The reference capacitor charges to the

reference voltage potential through SWR. A feedback

loop, closed around the integrator and comparator,

charges the CAZ capacitor with a voltage to compen-

sate for buffer amplifier, integrator and comparator

offset voltages (see Figure 3-2).

SWI

+IN

REF SWR

IN

SWZ

Analog

Common

SWI

IN

Analog

Input Buffer

+

RINT

–

CREF

SWIZ SWZ

CINT

CSZ

–

SWZ

+

Integrator

Comparator

+

– To

Digital

Section

SW1

Switch Open

Switch Closed

FIGURE 3-2:

System Zero Phase.

3.2.2

ANALOG INPUT SIGNAL

INTEGRATION

The TC7135 integrates the differential voltage between

the +INPUT and -INPUT pins. The differential voltage

must be within the device Common mode range; -1V

from either supply rail, typically. The input signal

polarity is determined at the end of this phase.

SWI

+IN

REF SWR

IN

SWZ

Analog

Common

SWI

IN

Analog

Input Buffer

+

RINT

CINT

–

CSZ

CREF

SWIZ SWZ

SWZ

–

Comparator

+

+

Integrator

–

To

Digital

Section

SW1

Switch Open

Switch Closed

FIGURE 3-3:

Phase.

Input Signal Integration

TC7135

3.2.3

REFERENCE VOLTAGE

INTEGRATION

The previously charged reference capacitor is con-

nected with the proper polarity to ramp the integrator

output back to zero (see Figure 3-4). The digital

reading displayed is:

EQUATION 3-3:

Reading

=

10,

000

-[--D----i--f--f-e---r--e---n---t--i-a---l----I--n---p---u---t--]

VREF

SWI

+IN

REF SWR

IN

SWZ

Analog

Common

SWI

IN

Analog

Input Buffer

+

RINT

CINT

CREF

–

SWIZ SWZ

SWZ

CSZ

–

Comparator

+

+

Integrator

–

To

Digital

Section

SW1

Switch Open

Switch Closed

FIGURE 3-4:

Reference Voltage

Integration Cycle.

3.2.4 INTEGRATOR OUTPUT ZERO

This phase ensures the integrator output is at 0V when

the system zero phase is entered. It also ensures that

the true system offset voltages are compensated for.

This phase normally lasts 100 to 200 clock cycles. If an

overrange condition exists, the phase is extended to

6200 clock cycles (see Figure 3-5).

SWI

+IN

SWR

REF

IN

SWZ

Analog

Common

SWI

IN

Analog

Input Buffer

+

RINT

CINT

CREF

–

SWIZ SWZ

SWZ

CSZ

–

Comparator

+

+

Integrator

–

To

Digital

Section

SW1

Switch Open

Switch Closed

FIGURE 3-5:

Phase.

Integrator Output Zero

 2004 Microchip Technology Inc.

DS21460C-page 7

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