TC7135 View Datasheet(PDF) - TelCom Semiconductor Inc => Microchip
Part Name
Description
Manufacturer
TC7135 Datasheet PDF : 13 Pages
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4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
TC7135
Table 2. Line Frequency Rejection
Oscillator Frequency
(kHz)
Frequency Rejected
(Hz)
300, 200, 150, 120,
100, 40, 33-1/3
250, 166-2/3,
125, 100
100
60
50
50, 60, 400
Table 3. Conversion Rate vs Clock Frequency
Conversion Rate
(Conv/Sec)
2.5
3.0
5.0
7.5
10.0
20.0
30.0
Clock
Frequency (kHz)
100
120
200
300
400
800
1200
Displays and Driver Circuits
TelCom Semiconductor manufactures three display de-
coder/driver circuits to interface the TC7135 to LCDs or LED
displays. Each driver has 28 outputs for driving four 7-
segment digit displays.
Device
TC7211AIPL
Package
40-Pin Epoxy
Description
4-Digit LCD Driver/Encoder
Several sources exist for LCDs and LED displays.
Manufacturer
Address
Display
Type
Hewlett Packard
Components
AND
Epson America, Inc.
640 Page Mill Road
Palo Alto, CA 94304
720 Palomar Ave.
Sunnyvale, CA 94086
3415 Kanhi Kawa St.
Torrance, CA 90505
LED
LCD and
LED
LCD
High-Speed Operation
The maximum conversion rate of most dual-slope ADCs
is limited by frequency response of the comparator. The
comparator in this circuit follows the integrator ramp with a
3 µs delay, and at a clock frequency of 160 kHz (6 µs period),
half of the first reference integrate clock period is lost in
delay. This means the meter reading will change from 0 to
1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 with 250 µV,
etc. This transition at midpoint is considered desirable by
most users; however, if clock frequency is increased appre-
ciably above 160 kHz, the instrument will flash "1" on noise
peaks even when the input is shorted.
For many dedicated applications, where the input signal
is always of one polarity, comparator delay need not be a
limitation. Since nonlinearity and noise do not increase
substantially with frequency, clock rates up to ~1 MHz may
be used. For a fixed clock frequency, the extra count (or
counts) caused by comparator delay will be constant and
can be digitally subtracted.
The clock frequency may be extended above 160 kHz
without this error, however, by using a low value resistor in
series with the integrating capacitor. The effect of the
resistor is to introduce a small pedestal voltage onto the
integrator output at the beginning of reference-integrate
phase. By careful selection of the ratio between this resis-
tor and the integrating resistor (a few tens of ohms in the
recommended circuit), the comparator delay can be com-
pensated for and maximum clock frequency extended
by approximately a factor of 3. At higher frequencies, ring-
ing and second-order breaks will cause significant
nonlinearities during the first few counts of the instrument.
The minimum clock frequency is established by leakage
on the auto-zero and reference capacitors. With most de-
vices, measurement cycles as long as 10 seconds give no
measurable leakage error.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the applications section. The multiplexed output
means if the display takes significant current from the logic
supply, the clock should have good PSRR.
Zero-Crossing Flip-Flop
The flip-flop interrogates data once every clock pulse
after transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by
clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
3-122
TELCOM SEMICONDUCTOR, INC.
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