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TC7135 View Datasheet(PDF) - TelCom Semiconductor Inc => Microchip

Part Name
Description
Manufacturer
TC7135
TelCom-Semiconductor
TelCom Semiconductor Inc => Microchip TelCom-Semiconductor
TC7135 Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
4-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTER
1
TC7135
POLARITY Output
A positive input is registered by a logic "1" polarity signal.
The POLARITY output (pin 23) is valid at the beginning of
reference integrate and remains valid until determined dur-
ing the next conversion.
The POLARITY bit is valid even for a zero reading.
Signals less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null applica-
tions.
Digit Drive Outputs
Digit drive outputs are positive-going signals. Their scan
sequence is D5, D4, D3, D2 and D1 (pins 12, 17, 18, 19 and
20, respectively). All positive signals are 200 clock pulses
wide, except D5, which is 201 clock pulses.
All five digits are continuously scanned, unless an
overrange condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse until
the beginning of the next reference-integrate phase. The
scanning sequence is then repeated, providing a blinking
visual display.
BCD Data Outputs
The binary coded decimal (BCD) outputs, B8, B4, B2 and
B1 (pins 16, 15, 14 and 13, respectively) are positive true-
logic signals. They become active simultaneously with digit
drive signals. In an overrange condition, all data bits are
logic "0".
APPLICATIONS INFORMATION
Component Value Selection
Integrating Resistor
The integrating resistor (RINT) is determined by the full-
scale input voltage and output current of the buffer used to
charge the integrator capacitor (CINT). Both the buffer ampli-
fier and the integrator have a Class A output stage, with 100
µA of quiescent current. A 20 µA drive current gives negli-
gible linearity errors. Values of 5 µA to 40 µA give good
results. The exact value of RINT for a 20 µA current is easily
calculated:
RINT =
Full-scale voltage .
20 µA
Integrating Capacitor
The product of RINT and CINT should be selected to give
the maximum voltage swing to ensure tolerance build-up will
not saturate integrator swing (approximately 0.3V from
either supply). For ±5V supplies, and analog common tied to
supply ground, a ±3.5V to ±4V full-scale integrator swing is
adequate. A 0.10 µF to 0.47 µF is recommended. In general,
the value of CINT is given by:
2
CINT =
[10,000 x clock period] x IINT
Integrator output voltage swing
(10,000) (clock period) (20 µA)
= Integrator output voltage swing .
3 A very important characteristic of the CINT is that it has
low dielectric absorption to prevent roll-over or ratiometric
errors. A good test for dielectric absorption is to use the
capacitor with the input tied to the reference. This ratiometric
condition should read half-scale 0.9999. Any deviation is
probably due to dielectric absorption. Polypropylene
capacitors give undetectable errors at reasonable cost.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
4
Auto-Zero and Reference Capacitors
The size of the auto-zero capacitor (CAZ) has some
influence on system noise. A large capacitor reduces noise.
The reference capacitor (CREF) should be large enough
such that stray capacitance from its nodes to ground is
negligible.
5 The dielectric absorption of CREF and CAZ is only impor-
tant at power-on, or when the circuit is recovering from an
overload. Smaller or cheaper capacitors can be used if
accurate readings are not required during the first few
seconds of recovery.
Reference Voltage
The analog input required to generate a full-scale output
6 is VIN = 2 VREF.
The stability of the reference voltage is a major factor in
overall absolute accuracy of the converter. Therefore, it is
recommended that high-quality references be used where
high-accuracy, absolute measurements are being made.
Suitable references are:
Part Type
Manufacturer
TC04
TelCom Semiconductor
TC05
TelCom Semiconductor
7
Conversion Timing
Line Frequency Rejection
A signal-integration period at a multiple of the 60 Hz line
frequency will maximize 60 Hz "line noise" rejection.
A 100 kHz clock frequency will reject 50 Hz, 60 Hz and
400 Hz noise, corresponding to 2.5 readings per second.
8
TELCOM SEMICONDUCTOR, INC.
3-121

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