FM93C86A View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
FM93C86A Datasheet PDF : 12 Pages
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Timing Diagrams (Continued)
ERASE CYCLE (ERASE)
CS
SK
DI
1 1 1 An An-1
A1 A0
tWP
Start Opcode
Address
DO
Bit
Bits(2) High - Z Bits(10/11)
Ready
Busy
93C86A (ORG=1; An=A9):
Address bits pattern -> A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined
93C86A (ORG=0; An=A10):
Address bits pattern -> A10-A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined
ERASE ALL CYCLE (ERAL)
CS
SK
DI
1 0 0 An An-1
A1 A0
tWP
Start Opcode
Address
DO
Bit
Bits(2) High - Z Bits(10/11)
Ready
Busy
93C86A (ORG=1; An=A9):
Address bits pattern -> 1-0-x-x-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1)
93C86A (ORG=0; An=A10):
Address bits pattern -> 1-0-x-x-x-x-x-x-x-x-x; (x -> Don’t Care, can be 0 or 1)
CLEARING READY STATUS
CS
SK
DI
High - Z
DO
Busy
Ready
Start
Bit
High - Z
Note: This Start bit can also be part of a next instruction. Hence the cycle
can be continued(instead of getting terminated, as shown) as if a new
instruction is being issued.
FM93C86A Rev. C.1
www.fairchildsemi.com
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