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APU428 View Datasheet(PDF) - APLUS INTEGRATED CIRCUITS

Part Name
Description
Manufacturer
APU428
Aplus
APLUS INTEGRATED CIRCUITS Aplus
APU428 Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
APU428
Predivider
The predivider is a 15-sage counter that uses PH0 as clock source. The output of T-FF is changed when the
input signal is changed from H to L. PH11~15 are reset to L when PLC 100H instruction is executed,
power-on reset or external reset is used. When PH14 is changed from H to L, the HALT release signal is
generated.
Alarm/frequency/melody
There is an 8-bit programmable counter and an 8-bit envelope control for alarm, frequency or melody output
from BZ/BZB.
The frequency counter can use software to select 1/2 duty, 1/3 duty,1/4 duty drive modes.
Frequency
1/2 Duty Frequency
1/3 Duty Frequency
1/4 Duty Frequency
INT function
The INT pin can be selected by mask option as pull-high/pull-low or none, and as a rising edge/falling edge
trigger.
Watchdog Timer
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
8/64/512 x PH10 (set by mask option). You can use software to enable and disable this function. The
watchdog enable flag will be disabled by power on reset or reset pin reset condition, but cannot be disabled
by watchdog reset itself.
HALT function
The HALT instruction disables all clocks except the predivider, timer, frequency counter, PWM, EL-light
generator and chattering clock in order to minimize the operating current.
STOP function
The STOP instruction disables all clocks to minimize the standby current, so only two external factors (INT,
IOA/IOC) can release the stop condition.
Instruction Table
Instruction
NOP
LCT Lz, Ry
Machine Code
0000 0000 0000 0000
0000 001Z ZZZZ YYYY
LCB Lz, Ry
0000 010Z ZZZZ YYYY
LCP Lz, Ry
0000 011Z ZZZZ YYYY
LCD Lz, @HL
0000 100Z ZZZZ 0000
OPA Rx
0000 1010 0XXX XXXX
OPAS Rx, D
0000 1011 DXXX XXXX
OPB Rx
0000 1100 0XXX XXXX
Function
No Operation
Lz Чʳ { 7SEG Чʳ Ry}
Lz Чʳ { 7SEG Чʳ Ry}
Lz Чʳ Ry , AC
Lz Чʳ T@HL
Port(A) Чʳ Rx
A1, 2, 3, 4 Чʳ Rx0, Rx1, D, Pulse
Port(B) Чʳ Rx
Flag/Remark
Preliminary
12
Ver. 0.0

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