UPD75P048GC-AB8 View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD75P048GC-AB8 Datasheet PDF : 40 Pages
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µPD75P048
SBI MODE (SCK: internal clock output (master))
Parameter
SCK Cycle Time
Symbol
Conditions
tKCY3
VDD = 4.5 to 6.0 V
SCK High-, Low-Level
tKL3
Widths
tKH3
SB0, 1 Set-Up Time
(vs. SCK ↑ )
SB0, 1 Hold Time
(vs. SCK ↑ )
SCK ↓→ SB0, 1 Output
Delay Time
tSIK3
tKSI3
tKSO3
SCK ↑→ SB0, 1 ↓
tKSB
SB0,1 ↓→ SCK
tSBK
SB0, 1 Low-Level Width tSBL
SB0, 1 High-Level Width tSBH
VDD = 4.5 to 6.0 V
RL = 1kΩ,
CL = 100pF
Note VDD = 4.5 to 6.0V
MIN.
1600
3800
tKCY3/2-50
tKCY3/2-150
TYP.
MAX.
150
Unit
ns
ns
ns
ns
ns
tKCY3/2
0
0
tKCY3
tKCY3
tKCY3
tKCY3
ns
250
ns
1000 ns
ns
ns
ns
ns
SBI MODE (SCK: external clock input (slave))
Parameter
Symbol
Conditions
MIN. TYP. MAX.
SCK Cycle Time
tKCY4
VDD = 4.5 to 6.0 V
800
3200
SCK Ligh-, Low-Level
tKL4
Widths
tKH4
VDD = 4.5 to 6.0 V
400
1600
SB0, 1 Set-Up Time
tSIK4
100
(vs. SCK ↑ )
SB0, 1 Hold Time
(vs. SCK ↑ )
SCK ↓→ SB0, 1 Output
Delay Time
tKSI4
tKSO4
RL = 1kΩ,
CL = 100pF
Note VDD = 4.5 to 6.0V
tKCY4/2
0
0
300
1000
SCK ↑→ SB0, 1 ↓
tKSB
tKCY4
SB0,1 ↓→ SCK ↓
tSBK
tKCY4
SB0, 1 Low-Level Width tSBL
tKCY4
SB0, 1 High-Level Width tSBH
tKCY4
Note RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
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