GS832018 View Datasheet(PDF) - Giga Semiconductor

Part Name

Description

Manufacturer

GS832018

2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs

Giga Semiconductor 

TQFP Pin Description

Symbol

A0, A1

A

DQA

DQB1

DQC

DQD

NC

BW

BA, BB

BC, BD

CK

GW

E1, E3

E2

G

ADV

ADSP, ADSC

ZZ

FT

LBO

VDD

VSS

VDDQ

Type

I

I

I/O

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Preliminary

GS832018/32/36T-250/225/200/166/150/133

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

Data Input and Output pins

No Connect

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Byte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.02 10/2004

5/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2003, GSI Technology

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