HI3-5700J-5 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
HI3-5700J-5 Datasheet PDF : 12 Pages
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HI-5700
rate.
reference voltage is the ideal location.
The signal source must absorb these transients prior to the Quarter Point Adjustment
end of the sample period to ensure a valid signal for
conversion. Suitable broad band amplifiers or buffers which
exhibit low output impedance and high output drive include
the HA-5004, HA-5002, and HA-5003.
The signal source may drive above or below the power supply
rails, but should not exceed 0.5V beyond the rails or damage
The reference tap points are brought out for linearity
adjustment or creating a nonlinear transfer function if
desired. It is not necessary to decouple the 1/4R, 1/2R, and 3/
4R tap points in most applications.
Power Supplies
may occur. Input voltages of -0.5V to +0.5 LSB are converted
to all zeroes; input voltages of VREF+ -0.5 LSB to VDD +0.5V
are converted to all ones with the Overflow bit set.
The HI-5700 operates nominally from 5V supplies but will
work from 3V to 6V. Power to the device is split such that
analog and digital circuits within the HI-5700 are powered
Full Scale Offset Error Adjustment
separately. The analog supply should be well regulated and
“clean” from significant noise, especially high frequency
In applications where accuracy is of utmost importance, noise. The digital supply should match the analog supply
three adjustments can be made; i.e., offset, gain, and within about 0.5V and should be referenced externally to the
reference tap point trims. In general, offset and gain analog supply at a single point. Analog and digital grounds
correction can be done in the preamp circuitry.
should not be separated by more that 0.5V. It is
Offset Adjustment
Offset correction can be done in the preamp driving the
converter by introducing a DC component to the input signal.
An alternate method is to adjust VREF- to produce the
desired offset. It is adjusted such that the 0 to 1 code
transition occurs at 0.5 LSB.
recommended that power supply decoupling capacitors be
placed as close to the supply pins as possible. A
combination of 0.01µF ceramic and 10µF tantalum
capacitors is recommended for this purpose as shown in the
test circuit.
Reducing Power Consumption
Gain Adjustment
Power dissipation in the HI-5700 is related to clock
frequency and clock duty cycle. For a fixed 50% clock duty
In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the VREF+ voltage. The
cycle, power may be reduced by lowering the clock
frequency. For a given conversion frequency, power may be
reduced by decreasing the Auto-Balance (φ1) portion of the
clock duty cycle. This relationship is illustrated in the
TABLE 3. CODE TABLE
CODE
DESCRIPTION
INPUT VOLTAGE †
VREF + = 4.0V
VREF - = 0.0V
(V)
DECIMAL
COUNT
OVF
MSB
D7
BINARY OUTPUT CODE
D6 D5 D4 D3
D2
LSB
D1
D0
Overflow (OVF)
4.000
511
1
1
1
1
1
1
1
1
1
Full Scale (FS)
3.9766
255
0
1
1
1
1
1
1
1
1
FS - 1 LSB
3.961
254
0
1
1
1
1
1
1
1
0
3/4 FS
2.992
192
0
1
1
0
0
0
0
0
0
1/2 FS
1.992
128
0
1
0
0
0
0
0
0
0
1/4 FS
0.992
64
0
0
1
0
0
0
0
0
0
1 LSB
0.0078
1
0
0
0
0
0
0
0
0
1
Zero
0
0
0
0
0
0
0
0
0
0
0
† The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
4-1500
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