HIP2120 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
HIP2120 Datasheet PDF : 16 Pages
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HIP2120, HIP2121
Pin Descriptions
10 LD
1
9 LD
1
2
3
3
4
4
5
8
8
7
7
9
9
10
10
5
-
6
6
-
-
SYMBOL
VDD
HB
HO
HS
PWM
EN
VSS
LO
NC
RDT
EPAD
DESCRIPTION
Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to
VSS.
High-side bootstrap supply voltage referenced to HS. Connect the positive side of the
bootstrap capacitor to this pin. Bootstrap diode is on-chip.
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect
negative side of bootstrap capacitor to this pin.
PWM input. For PWM = 1, HO = 1 and LO = 0. For PWM = 0, HO = 0 and LO = 1.
Output enable, when low, HO = LO = 0
Negative voltage supply, which will generally be ground.
Low-side output. Connect to gate of low-side power MOSFET.
No Connect. This pin is isolated from all other pins.
A resistor connected between this pin and VSS adds additional delay time to the falling and
rising edges of the PWM input.
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other
pins.
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
PART
MARKING
INPUT
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
HIP2120FRTAZ
HIP 2120AZ
CMOS
-40 +125
10 Ld 4x4 TDFN
L10.4x4
HIP2121FRTAZ
HIP 2121AZ
3.3V/TTL
-40 +125
10 Ld 4x4 TDFN
L10.4x4
HIP2120FRTBZ (Note 3)
HIP 2120BZ
CMOS
-40 +125
9 Ld 4x4 TDFN
L9.4x4
HIP2121FRTBZ (Note 3)
HIP 2121BZ
3.3V/TTL
-40 +125
9 Ld 4x4 TDFN
L9.4x4
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted
for additional spacing.
4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2120, HIP2121. For more information on MSL please see tech brief
TB363.
3
FN7668.0
December 23, 2011
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