HM-6504/883 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
HM-6504/883 Datasheet PDF : 10 Pages
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HM-6504/883
March 1997
4096 x 1 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high perfor-
mance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
PACKAGE TEMPERATURE RANGE
200ns
CERDIP
-55oC to +125oC
HM1-6504B/883
300ns
HM1-6504/883
PKG. NO
F18.3
Pinout
HM-6504/883 (CERDIP)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
Q7
W8
GND 9
18 VCC
17 A6
16 A7
15 A8
14 A9
13 A10
12 A11
11 D
10 E
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W Write Enable
D
Data Input
Q
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-134
File Number 2993.1
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