HSDL-7001-2500(1996) View Datasheet(PDF) - HP => Agilent Technologies

Part Name

Description

Manufacturer

HSDL-7001-2500
(Rev.:1996)

IR 3/16 Encode/Decode IC

HP => Agilent Technologies 

Encoding Scheme

16 CYCLES

16XCLK

16 CYCLES

16 CYCLES

16 CYCLES

TXD

IRTXD

7 CS

3 CS

The encoding scheme relies on a

clock being present, which is set

to 16 times the data transmission

baud rate (16XCLX). The encoder

sends a pulse for every space or

“0” that is sent on the TXD line.

On a high to low transition of the

TXD line, the generation of the

pulse is delayed for 7 clock cycles

of the 16XCLK before the pulse is

set high for 3 clock cycles (or

3/16th of a bit time) and then

subsequently pulled low. This

generates a 3/16th bit time pulse

centered around the bit of

information (“0”) that is being

transmitted.

For consecutive spaces, pulses

with a 1 bit time delay are gener-

ated in series. If a logic 1 (mark)

is sent then the encoder does not

generate a pulse.

Decoding Scheme

16XCLK

16 CYCLES

16 CYCLES

16 CYCLES

16 CYCLES

IRRXD

RXD

3 CS

The IrDA-SIR (Serial InfraRed)

decoding modulation method can

be thought of as a pulse stretch-

ing scheme.

Every high to low transition of

the IR_RXD line signifies the

arrival of a pulse. This pulse

needs to be stretched to

accommodate 1 bit time (or 16

16XCLK cycles). Every pulse that

is received is translated into a “0”

or space on the RXD line equal to

1 bit time.

Note 1: The stretched pulse must

be at least 3/4 of a bit time in

duration to be correctly inter-

preted by a UART.

Note 2: It is recommended that

TXD remains high when not

transmitting. This ensures the

LED is off and will not interfere

with signal reception.

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