HT45F4M View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
Manufacturer
HT45F4M Datasheet PDF : 138 Pages
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HT45F4M
Lithium Battery Backup Power ASSP MCU
On-Chip Debug Support – OCDS
An EV chip exists for the purposes of device emulation. This EV chip device also provides an
“On-Chip Debug” function to debug the device during the development process. The EV chip
and the actual MCU devices are almost functionally compatible except for the “On-Chip Debug”
function. Users can use the EV chip device to emulate the real chip device behavior by connecting
the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is
the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin.
When users use the EV chip for debugging, other functions which are shared with the OCDSDA
and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two
OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory
programming pins for ICP. For a more detailed OCDS description, refer to the corresponding
document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.
Holtek e-Link Pins
OCDSDA
OCDSCK
VDD
GND
EV Chip Pins
OCDSDA
OCDSCK
VDD
VSS
Pin Description
On-Chip Debug Support Data/Address input/output
On-Chip Debug Support Clock input
Power Supply
Ground
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some
remain protected from user manipulation. The second area of Data Memory is known as the General
Purpose Data Memory, which is reserved for general purpose use. All locations within this area are
read and write accessible under program control.
The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are
accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible
in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer
to the correct value. The start address of the Data Memory for the device is the address 00H.
Rev. 1.10
21
January 15, 2013
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