HT49RV5 View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
Manufacturer
HT49RV5 Datasheet PDF : 48 Pages
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HT49RV5/HT49CV5
Functional Description
Execution Flow
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme ensures that instructions are ef-
fectively executed in one cycle. Exceptions to this are in-
structions that change the contents of the program
counter, such as subroutine calls or jumps, in which
case, two cycles are required to complete the instruc-
tion.
Program Counter - PC
The 12-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 4096
addresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, etc., the microcontroller manages program
control by loading the address corresponding to each in-
struction.
For conditional skip instructions, once the condition has
been met, the next instruction, which has already been
fetched during the current instruction execution, is dis-
carded and a dummy cycle replaces it while the proper
instruction is obtained. Otherwise proceed with the next
instruction.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Program Counter
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset
000000000000
External Interrupt 0
000000000100
External Interrupt 1
000000001000
Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 1 1 0 0
Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 1 0 0 0 0
Serial Interface Interrupt
000000010100
Multi-function Interrupt
000000011000
Skip
Program Counter+2
Loading PCL
*11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
#11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
Program Counter
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.20
7
April 14, 2006
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