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HT82V38 View Datasheet(PDF) - Holtek Semiconductor

Part Name
Description
Manufacturer
HT82V38
Holtek
Holtek Semiconductor Holtek
HT82V38 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Symbol
Parameter
Serial Interface
fSCLK
Maximum SCLK Frequency
tLS
SLOAD to SCLK Setup Time
tLH
SCLK to SLOAD Hold Time
tDS
SDATA to SCLK Rising Setup Time
tDH
SCLK Rising to SDATA Hold Time
tRDV
SCLK Falling to SDATA Valid
Data Output
tOD
Output Delay (output load 10pF)
Latency (Pipeline Delay)
HT82V38
Min.
Typ.
Max.
Unit
10
¾
¾
MHz
10
¾
¾
ns
10
¾
¾
ns
10
¾
¾
ns
10
¾
¾
ns
10
¾
¾
ns
¾
10
¾
ns
¾
9
¾
Cycles
Functional Description
Integral Nonlinear (INL)
Integral nonlinearity error refers to the deviation of each
individual code from a line drawn from ²zero scale²
through ²positive full scale². The point used as ²zero
scale² occurs 1/2 LSB before the first code transition.
²Positive full scale² is defined as a level 1/2 LSB beyond
the last code transition. The deviation is measured from
the middle of each particular code to the true straight
line.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed to 16-bit resolution indicates that all
4096 codes, respectively, must be present over all oper-
ating ranges.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage. The offset
error is the deviation of the actual first code transition
level from the ideal level.
Gain Error
The last code transition should occur for an analog
value 1/2 LSB below the full-scale voltage
(2´(REFT-REFB)). Gain error is the deviation of the ac-
tual difference between first and last code transitions
and the ideal difference between the first and last code
transitions.
Aperture Delay
The aperture delay is the time delay that occurs from
when a sampling edge is applied to the HT82V38 until
the actual sample of the input signal is held. Both
CDSCLK1 and CDSCLK2 sample the input signal dur-
ing the transition from high to low, so the aperture delay
is measured from each clock¢s falling edge to the instant
the actual internal sample is taken.
Rev. 1.00
5
July 23, 2009

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